As a DFX Architect, you will be the technical authority for Altera’s next-generation FPGA and SoC families. You will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost (TCO), and accelerate Time-to-Market (TTM). This is a high-visibility leadership role requiring collaboration with Silicon Architecture, Physical Design, and Post-Silicon Manufacturing teams across global sites.
Key Responsibilities
Architectural Strategy: Define and document DFX architectures for multi-die (chiplet) systems, high-speed transceivers, and massive FPGA fabrics.
Technology Leadership: Drive the adoption of advanced DFX features such as IEEE 1687 (IJTAG), IEEE 1838 (3D-IC), and High-Speed Link Testing (HSLT).
Test Cost Optimization: Develop strategies to reduce Test Data Volume (TDV) and Test Application Time (TAT) through advanced compression and adaptive testing techniques.
Debug Architecture: Lead the definition of on-chip debug infrastructures (e.g., logic analyzers, trace buffers, and scan-dump) to enable rapid root-cause analysis of complex silicon failures.
Cross-Functional Influence: Partner with Silicon Design Architects, Manufacturing and Post-Silicon System Debug experts to drive DFT and DFD feature requirements are baked into the hardware specifications as landing zone features
Tool & Flow Roadmap: Influence EDA vendors (Synopsys, Siemens/Mentor, Cadence) to align their roadmaps with Altera’s specific FPGA architectural needs.
Mentorship: Act as a technical beacon for the Penang engineering site, mentoring senior and staff engineers to elevate the organization's technical depth.
Education
BS/MS or Ph.D. in Electrical/Electronics/Computer Engineering or a related field
Technical Requirements
Proven Track Record: Minimum 10–12 years of hands-on experience in DFT/DFD, with at least 4 years in an architectural or lead capacity. Familiar with the semiconductor end-to-end product life cycle for ASIC and FPGA
Advanced DFT Concepts: Deep expertise in Hierarchical DFT, Logic/Memory BIST, Scan Compression (EDT), Boundary Scan, JTAG/iJTAG and other established DFT standards.
Multi-Die/Chiplet Knowledge: Experience with 2.5D/3D packaging technologies and the specific DFX challenges associated with interposers and TSVs.
Silicon Debug: Expert knowledge of silicon bring-up, failure analysis, and the use of DFD hooks for in-system hardware/firmware co-debugging.
FPGA Architecture: (Highly Preferred) Specific understanding of FPGA-specific testing, such as configuration RAM testing and programmable interconnect verification.
Safety Standards: Proven experience in designing DFX architectures that meet ASIL-D (Automotive Safety Integrity Level) and other industrial functional safety standard requirements on semiconductor products
EDA & Tool Standards
Expertise in Tessent (Siemens), DesignCompiler/DFTMAX (Synopsys), or equivalent industry-leading suites.
Deep familiarity with IEEE standards (1149.1, 1149.6, 1500, 1687, 1838).
Proficiency in scripting (Tcl/Python) to build custom architectural modeling or validation tools.
Leadership & Soft Skills
Strategic Thinking: Ability to balance technical perfection with business constraints (die area overhead vs. test coverage).
Stakeholder Management: Experience presenting complex technical roadmaps to executive leadership and global stakeholders.
Problem Solving: A reputation for resolving "mission-critical" silicon issues that bridge design and manufacturing.
Skills Required
- Minimum 10-12 years of hands-on experience in DFT/DFD
- At least 4 years in an architectural or lead capacity
- Proficiency in scripting (Tcl/Python)
- Deep expertise in Hierarchical DFT
- Experience with 2.5D/3D packaging technologies
- Expert knowledge of silicon bring-up and failure analysis
- Proven experience in designing DFX architectures that meet ASIL-D
- Expertise in Tessent or equivalent industry-leading suites
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
