DFT Verification Engineer

This role is for one of the Weekday's clients

Salary range: Rs 600000 - Rs 2000000 (ie INR 6-20 LPA)

Min Experience: 5+ years

Location: Bengaluru

JobType: full-time

We are looking for an experienced DFT Verification Engineer to join our VLSI design team and drive the verification of Design-for-Test (DFT) architectures for complex SoC designs. In this role, you will be responsible for verifying scan logic, ATPG, MBIST, JTAG, and boundary scan implementations to ensure high fault coverage, robust testability, and production-ready silicon quality.

You will collaborate closely with Design, DFT, Physical Design, and Verification teams to validate DFT functionality, debug issues, and ensure successful verification closure across the chip development lifecycle.

• Verify DFT logic including scan chains, scan compression, ATPG, MBIST, JTAG, TAP controllers, and boundary scan using simulation-based verification.
• Validate DFT architectures and ensure correct implementation across complex SoC designs.
• Perform functional verification of DFT control logic and test modes.
• Review DFT specifications and ensure implementation aligns with design requirements.

• Execute gate-level simulations (GLS) with SDF back-annotation to verify timing accuracy and DFT functionality.
• Debug DFT-related failures and perform root cause analysis in collaboration with cross-functional teams.
• Validate scan chain integrity, chain continuity, clock domain interactions, and test logic behavior.
• Ensure proper implementation of scan compression, X-masking, and clock domain constraints.

• Support Automatic Test Pattern Generation (ATPG) validation and review fault coverage metrics.
• Verify test control logic and production test readiness.
• Review DFT verification results, identify coverage gaps, and recommend improvements.
• Participate in DFT sign-off activities to ensure high manufacturing test quality.

• Develop and maintain automation scripts for DFT verification and regression flows.
• Improve verification efficiency using Perl, Python, or Shell scripting.
• Contribute to verification methodology enhancements and process improvements.
• Maintain documentation for verification plans, test cases, and sign-off reports.

• Bachelor's or Master's degree in Electronics, VLSI, Computer Engineering, or a related discipline.
• 5–8 years of hands-on experience in DFT Verification for complex ASIC/SoC designs.
• Strong understanding of:
• Scan Architecture
• Automatic Test Pattern Generation (ATPG)
• MBIST
• JTAG (IEEE 1149.1)
• Boundary Scan
• Scan Compression
• Test Control Logic
• Experience with industry-standard DFT tools such as:
• Synopsys TetraMAX
• Siemens/Mentor Tessent
• Mentor ATPG
• Experience with HDL simulation tools including:
• Synopsys VCS
• Cadence Xcelium
• Siemens Questa
• Good understanding of Static Timing Analysis (STA) constraints and their impact on DFT implementation.
• Strong debugging and problem-solving skills.
• Experience with scripting languages such as Python, Perl, or Shell for automation.

• Experience with UVM or OVM verification methodologies.
• Familiarity with SoC verification environments and verification closure processes.
• Experience working on advanced process nodes.
• Knowledge of silicon bring-up, post-silicon validation, or production testing is an advantage.

The ideal candidate:

• Has deep expertise in DFT verification and production test methodologies.
• Enjoys debugging complex silicon verification challenges.
• Collaborates effectively with Design, DFT, Physical Design, and Verification teams.
• Takes ownership of verification quality and sign-off.
• Is detail-oriented with a strong focus on test coverage, silicon reliability, and manufacturing readiness.

• Automatic Test Pattern Generation (ATPG)
• Scan Insertion
• DFT Verification
• Scan Architecture
• Gate-Level Simulation (GLS)
• Static Timing Analysis (STA)

• MBIST
• JTAG
• Boundary Scan
• Synopsys TetraMAX
• Siemens Tessent
• UVM
• Python
• Perl
• Shell Scripting