About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities:
- Implement and Validate MBIST, Scan and LBIST on various Processor Core IP Subsystems.
- Work closely with RTL Designers to implement Shared Bus/Multi-Memory Bus MBIST.
- Implement DFT Scan structures including Streaming Scan Fabric, OCC, Scan Compression.
- Implement LBIST (Logic-BIST) on the Automotive/FuSa designs and perform verification of In-System Test mode implementation.
- Perform ATPG and LBIST Pattern generation and Coverage analysis.
- Validate all DFT Structures through RTL and Gate Level Simulations.
- DFT Timing Constraints generation and support STA.
- Ensuring ambitious performance, power, and area (PPA) goals are met on DFT inserted CPU designs.
- Contributing to DFT implementation flow development to drive best-in-class automation.
Requirements
- 5+ years of DFT experience with multiple tape outs.
- Experience with RTL level DFT IP Insertion and Verification.
- Experience on MBIST Insertion and verification at Block or SoC level.
- Experience with Scan Compression, ATPG, Coverage analysis and GLS.
- Below experiences are a strong plus but not mandatory
- o Experience on Shared Bus MBIST
- o Experience with Streaming Scan Fabric or Streaming Scan Network (SSN) implementations.
- o Experience with CPU DFT Implementation
- o Experience on LBIST
- o Understanding of logic design and CPU architecture
- Attention to detail and a focus on high-quality design.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Top Skills
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
