Design Verification Lead Engineer

Reposted 20 Days Ago
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Austin, TX, USA
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead the execution and management of verification projects, ensuring comprehensive test coverage for CPU cores or processor blocks through diverse technical tasks.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Verification Lead Engineer

Role Overview:
The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.

Key Responsibilities:

  • Technical Execution: Developing and executing detailed verification plans (vPlans) using Cadence vManager.
  • Environment Development: Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
  • Debug & Triage: Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
  • Regression Management: Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
  • Project Tracking: Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.

Required Qualifications:

  • B.S/M.S in EEE with 5–8+ years of hands-on experience in VLSI design verification.
  • Strong command of SystemVerilog Assertions (SVA), constraint randomization, and UVM.
  • Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
  • Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • B.S/M.S in EEE
  • 5-8+ years of hands-on experience in VLSI design verification
  • Strong command of SystemVerilog Assertions, constraint randomization, and UVM
  • Experience with processor integration (e.g., RISC-V or ARM)
  • Expertise in scripting for flow automation (Perl, Python, or Tcl)
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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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