Job Description
Understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.
Required experience
- Understanding of SV/UVM.
- Good knowledge of Verilog/Vhdl/C/C++
- Experience in any scripting language Perl/Python/Shell.
- Good debugging skills.
Desirable skills and experience
- Familiarity with ARM/CPU architectures.
- Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
- Knowledge of AMBA protocols. (AXI/AHB/APB).
- Hands on experience in writing tests/sequences/functional coverage.
- Prior experience with Cadence verification tools and flows is highly desirable.
Strong vocabulary, communication, planning, and presentation skills are essential. Ability to work with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing to take up additional responsibilities to contribute to team’s success.
We’re doing work that matters. Help us solve what others can’t.Similar Jobs
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
