Design Verification Intern - Master's Degree

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Custom Cloud Solutions Engineering ASIC Design Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise applications. As a member of the ASIC Design Verification team, you will have the opportunity to develop and grow your skills in the areas verification testbench with UVM Methodology, verification component design and testing of specific system-on-a-chip (SOC) designs at block/cluster/full chip levels.

What You Can Expect

• Verifying complex SoCs through simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes
• Collaborate closely with design and other verification engineers to develop and implement verification test plans and drive verification methodology work
• Develop constrained-random verification test environment using Verilog/System Verilog, UVM and C programming, including testbenches, checkers, monitors, drivers and and other testbench components
• Use problem solving skills to debug failing simulations and create test vectors and testing scenarios to exhaustively exercise a design
• Drive and analyze test coverage metrics
• Utilizes technical abilities and sound communication skills to implement and manage verification deliverables to customers

What We're Looking For

• Currently pursuing a Bachelor’s or Master's Degree in Computer Science, Electrical Engineering, or related fields
• Knowledge of advance digital design, CPU design and computer architecture
• Experience with industry standard simulators such as Cadence Incisive, Synopsys VCS or Questasim
• Experience with HDLs such as VHDL, Verilog or SystemVerilog
• Experience in standard verification methodology flows, including developing test plans, building testbenches and generating test cases
• Experience programming in C or C++ and in scripting using Python, PERL or Bash
• Experience with industry standard interfaces and peripherals
• Great problem solving and critical thinking skills
• Good written and verbal communication skills
• Self-starter, goal oriented and a team player

Expected Base Pay Range (USD)

27 - 53, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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