At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, communications, automotive, and edge computing. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of programmable logic.
About the Role
As a Design Verification Engineer at Altera, you will play a key role in ensuring the functional correctness and quality of next-generation FPGA and SoC products. You will develop and execute comprehensive verification strategies for complex digital designs, collaborating closely with architecture, RTL design, physical design, firmware, and software teams throughout the product development lifecycle.
This position offers the opportunity to work on cutting-edge programmable logic technologies while leveraging industry-leading verification methodologies, constrained-random verification, coverage-driven verification, and assertion-based verification to deliver world-class semiconductor products.
Key Responsibilities:
Develop and execute block-level and subsystem-level verification plans for complex FPGA and SoC designs.
Create reusable SystemVerilog and UVM-based verification environments, agents, sequences, scoreboards, and checkers.
Develop constrained-random and directed test cases to verify digital logic functionality and achieve functional coverage goals.
Create and maintain assertions using SystemVerilog Assertions (SVA) to improve design quality and identify functional issues early.
Debug simulation failures, functional bugs, and RTL issues by working closely with RTL designers, architects, and firmware engineers.
Perform coverage analysis including functional, code, toggle, and assertion coverage to ensure verification completeness.
Develop verification infrastructure, automation, and regression environments to improve engineering productivity.
Participate in design reviews, verification reviews, and bug triage meetings throughout the development lifecycle.
Collaborate with emulation, FPGA prototyping, post-silicon validation, and software teams to support product bring-up and validation.
Contribute to continuous improvement of verification methodologies, reusable verification IP, and engineering best practices.
Salary Range
The pay range below is for Bay Area, California only. Actual salary may vary based on job location, job-related knowledge, skills, experience, training, and other factors. We also offer incentive opportunities that reward employees based on individual and company performance.
$100,000 - $120,000 USD
We use artificial intelligence to screen, assess, or select applicants for this position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline with 4+ years of industry experience in digital design verification, ASIC verification, FPGA verification, or SoC verification, including the following:
4+ years of experience verifying digital ASIC, FPGA, or SoC designs using SystemVerilog and Universal Verification Methodology (UVM).
4+ years of experience developing constrained-random and directed verification testbenches for complex digital designs.
3+ years of experience writing SystemVerilog Assertions (SVA) and applying assertion-based verification methodologies.
3+ years of experience using industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent simulators.
3+ years of experience debugging RTL functional issues using waveform analysis, simulation debugging tools, and verification methodologies.
3+ years of experience developing verification components including UVM agents, drivers, monitors, scoreboards, sequences, and functional coverage models.
3+ years of experience analyzing functional coverage, code coverage, assertion coverage, and coverage closure metrics.
2+ years of experience using scripting languages such as Python, Perl, Tcl, Shell, or similar languages to automate verification workflows and regression environments.
2+ years of experience using revision control systems such as Git, Perforce, or equivalent version control tools.
2+ years of experience collaborating with RTL design, architecture, physical design, firmware, or software engineering teams throughout the product development lifecycle.
1+ year of experience developing automated regression environments and analyzing regression results to improve verification quality and productivity.
1+ year of experience verifying one or more high-speed digital interfaces such as PCIe, Ethernet, DDR, LPDDR, HBM, AXI, AMBA, USB, CXL, or similar industry-standard protocols.
Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
6+ years of experience in ASIC, FPGA, or SoC design verification.
Experience verifying complex FPGA architectures, programmable logic devices, or configurable hardware systems.
Experience verifying high-speed interfaces including PCIe Gen4/Gen5, Ethernet, DDR4/DDR5, LPDDR, HBM, CXL, or SerDes protocols.
Experience with formal verification tools and methodologies.
Experience with hardware emulation platforms, FPGA prototyping, or acceleration-based verification.
Experience developing reusable verification IP (VIP) for complex semiconductor products.
Experience with low-power verification methodologies including UPF, CPF, retention, isolation, and power-aware simulation.
Experience using lint, CDC, RDC, or static verification tools.
Experience with post-silicon validation, silicon bring-up, or hardware/software co-verification.
Experience applying coverage-driven verification methodologies to large-scale ASIC or FPGA programs.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline
- 4+ years verifying digital ASIC, FPGA, or SoC designs using SystemVerilog and UVM
- 4+ years developing constrained-random and directed verification testbenches
- 3+ years writing SystemVerilog Assertions (SVA) and using assertion-based verification
- 3+ years using simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim
- 3+ years debugging RTL functional issues using waveform analysis and simulation tools
- 3+ years developing verification components (UVM agents, drivers, monitors, scoreboards, sequences) and functional coverage models
- 3+ years analyzing functional, code, toggle, and assertion coverage and achieving coverage closure
- 2+ years using scripting languages (Python, Perl, Tcl, Shell) to automate verification workflows
- 2+ years using revision control systems (Git, Perforce)
- 2+ years collaborating with RTL design, architecture, physical design, firmware, or software teams during product development
- 1+ year developing automated regression environments and analyzing regression results
- 1+ year verifying high-speed digital interfaces (PCIe, Ethernet, DDR/LPDDR/HBM, AXI/AMBA, USB, CXL, SerDes)
- Master's degree in EE/CE/CS or related discipline
- 6+ years experience in ASIC, FPGA, or SoC design verification
- Experience verifying complex FPGA architectures, programmable logic, or configurable hardware systems
- Experience with formal verification tools and methodologies
- Experience with hardware emulation platforms, FPGA prototyping, or acceleration-based verification
- Experience developing reusable verification IP (VIP) for complex semiconductor products
- Experience with low-power verification methodologies (UPF, CPF, retention, isolation) and power-aware simulation
- Experience using lint, CDC, RDC, or static verification tools
- Experience with post-silicon validation, silicon bring-up, or hardware/software co-verification
- Experience applying coverage-driven verification methodologies to large-scale ASIC or FPGA programs
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
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