Design Verification Engineer (PMU Verification - Modem Subsystem)

Posted 19 Days Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Mid level
Artificial Intelligence • HR Tech • Professional Services • Software
The Role
Design and execute SystemVerilog/UVM verification for PMU blocks in the modem subsystem, create verification plans and tests, perform GLS and low-power verification, debug RTL/testbench failures, close functional coverage, and collaborate with RTL designers to resolve issues while meeting timelines.
Summary Generated by Built In

This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru

JobType: full-time


RequirementsJob Responsibilities:
  • Perform Design Verification of Power Management Unit (PMU) blocks in the Modem Subsystem.
  • Develop and execute SystemVerilog/UVM-based verification environments, testcases, and regression suites.
  • Create verification plans and ensure functional coverage closure.
  • Debug RTL, testbench, and simulation failures efficiently.
  • Perform Gate-Level Simulations (GLS) and analyze timing-related issues.
  • Verify low-power functionality and power management features.
  • Work closely with RTL designers to resolve design and verification issues.
  • Ensure high-quality verification deliverables while meeting project timelines.
Mandatory Skills:
  • Strong hands-on experience in SystemVerilog (SV) and UVM.
  • Good understanding of Digital Design fundamentals.
  • Experience in Power Management Unit (PMU) verification or Low-Power Verification.
  • Understanding of IESNLP methodology/concepts.
  • Experience with Gate-Level Simulations (GLS).
  • Knowledge of functional coverage, assertions, and debugging techniques.
  • Good problem-solving and communication skills.
Must-have skills

Power Management Unit, SystemVerilog, Universal Verification Methodology - UVM

Good-to-have skills

Digital Design fundamentals, Gate-Level Simulations

Skills Required

  • 4+ years verification experience
  • Strong hands-on experience in SystemVerilog
  • Strong hands-on experience in UVM
  • Power Management Unit (PMU) verification or Low-Power Verification experience
  • Understanding of IESNLP methodology/concepts
  • Experience with Gate-Level Simulations (GLS)
  • Knowledge of functional coverage, assertions, and debugging techniques
  • Good understanding of Digital Design fundamentals
  • Ability to debug RTL, testbench, and simulation failures
  • Good problem-solving and communication skills
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The Company
Year Founded: 2021

What We Do

Weekday is an AI-powered recruitment platform that helps startups hire top-tier engineering and product talent. By leveraging a massive database of white-collar professionals and advanced outreach tools, the company streamlines the hiring process through automated sourcing, AI-driven resume screening, and white-glove contingency services. Their mission is to modernize recruitment by enabling companies to discover and engage passive candidates efficiently, ensuring high-quality hires for critical roles.

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