The Role
Design Verification Engineer specializing in IP Verification with expertise in SystemVerilog and UVM. Responsible for verifying IP-level components such as PCIe, Ethernet, DMA, and DSP Data path. Proficient in scripting languages like Perl and Python.
Summary Generated by Built In
Vision:
Establishing a world-class semiconductor and wireless systems company headquartered in India to address the expanding requirements for advanced connectivity, computing, and security for wireless 5G and 6G infrastructure and devices. Our product offerings including Intellectual Property (IP), chip design, semiconductor products, software and systems developed and owned in India. Drawing inspiration from industry giants like Qualcomm and MediaTek, we aim to become the leader in wireless semiconductor and systems player in India and worldwide.
Key Points:
- PhD, Master's, or Bachelor's degree in Electronics or Computer Engineering
- 5+ years of industry experience
- Expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM)
- Knowledge of C/C++ is desirable
- Proven experience with multiple tape-outs, including various aspects of testbench/BFM development and test automation
- Strong understanding of AMBA/AXI protocols
- Experience with IP-level verification of one or more of the following:
- Interface/Networking IPs such as PCIe, Ethernet (MAC and PCS), JESD, DDR
- NOC Interconnects
- DMA, Interrupt Controllers, etc.
- DSP Data path
- Proficiency in scripting languages such as Perl or Python
Why Join Us:
- Opportunity to work on cutting-edge telecommunications technologies.
- Collaborative and innovative work environment.
- Competitive salary and benefits package.
- Professional growth and development opportunities.
Top Skills
C
C++
Systemverilog
The Company
What We Do
Silicon and software for 5G
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