Design Verification Engineer (IP DV)

This role is for one of the Weekday's clients

Salary range: Rs 800000 - Rs 2000000 (ie INR 8-20 LPA)

Experience: 2+ yrs

Location: Bengaluru, Karnataka, India

Job Type: Full-Time

We are looking for a skilled Design Verification Engineer with strong expertise in SoC/IP Verification, SystemVerilog, and UVM to validate complex digital designs and ensure high-quality silicon delivery. This role is ideal for professionals who are passionate about functional verification, verification methodology development, and solving challenging design problems in advanced semiconductor environments.

As a Design Verification Engineer, you will be responsible for developing robust verification environments, creating reusable testbenches, executing comprehensive verification plans, and ensuring functional correctness of IPs and SoCs. Working closely with RTL designers, architects, and cross-functional engineering teams, you will play a key role in achieving verification closure through constrained random testing, functional coverage analysis, assertions, and systematic debugging. This position offers an opportunity to work on cutting-edge semiconductor technologies while contributing to high-performance and reliable chip development.

• Develop, enhance, and maintain reusable UVM-based verification environments for IP and SoC verification.
• Create and execute detailed verification plans, test cases, and verification strategies based on design specifications.
• Build scalable SystemVerilog testbenches using industry-standard verification methodologies.
• Perform functional verification of complex digital designs using constrained random verification techniques.
• Develop assertions (SVA), checkers, scoreboards, monitors, and coverage models to improve verification quality.
• Analyze functional coverage metrics and drive verification closure by identifying coverage gaps.
• Verify AMBA-based interfaces including AXI, AHB, and APB protocols.
• Debug simulation failures, analyze waveform results using tools such as Verdi, and collaborate with RTL teams to resolve design issues.
• Execute regression testing, review verification results, and ensure design quality before tape-out.
• Work with simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim for verification execution.
• Participate in design reviews, verification reviews, and technical discussions to improve overall product quality.
• Maintain verification documentation and contribute to continuous improvement of verification methodologies and reusable components.

• 2–5 years of experience in Design Verification or SoC/IP Verification.
• Strong hands-on expertise in SystemVerilog, UVM, and modern verification methodologies.
• Experience developing reusable verification environments and comprehensive UVM testbenches.
• Solid understanding of AMBA protocols including AXI, AHB, and APB.
• Strong knowledge of constrained random verification, functional coverage, assertions (SVA), and coverage-driven verification.
• Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.
• Proficiency in debugging complex verification issues using waveform debugging tools such as Verdi.
• Good understanding of digital design, RTL concepts, and semiconductor design flows.
• Strong analytical, debugging, and problem-solving skills with attention to detail.
• Excellent communication and collaboration skills, with the ability to work effectively in cross-functional engineering teams and deliver high-quality verification solutions.