Design Engineering Manager – Power Management

Posted 3 Hours Ago
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Hiring Remotely in Home, Klouékanmè, Kouffo, BEN
Remote
Senior level
Semiconductor • Manufacturing
The Role
Lead IC design for next-generation power management: architect high-voltage gate drivers, IPMs, and silicon capacitors; perform transistor-level analog/mixed-signal design, supervise layout through tape-out, and validate first-silicon with test engineering while mentoring junior engineers.
Summary Generated by Built In

Job Description:

Design Engineering Manager – Power Management (Gate Drivers, IPMs, & Silicon Capacitors)

Location: Remote

Role Overview

We are seeking a highly skilled Lead IC Design Engineer to architect and design our next-generation Power Management ICs. In this role, you will serve as the primary technical authority for the development of high-performance Gate Drivers, Intelligent Power Modules (IPMs), and advanced Silicon Capacitor technologies. You will drive the hands-on execution of analog and mixed-signal designs, define block-level architectures, and provide technical mentorship to junior design and layout engineers to deliver market-leading power solutions. This high visibility role involves extensive interaction with management and cross-functional teams, such as Device Engineering, System Applications, and Packaging

Key Responsibilities

  • Technical Architecture: Define and architect high-voltage gate drivers, IPM protection circuits, and integrated silicon capacitor structures.
  • Hands-On Design: Perform transistor-level design, simulation, and verification of complex analog and mixed-signal power blocks.
  • Silicon Integration: Lead the integration of passive silicon capacitors into advanced multi-chip modules and system-in-package topologies.
  • Technical Mentorship: Provide technical guidance, code reviews, and design verification oversight to junior and mid-level engineering staff.
  • Tape-Out Ownership: Drive the execution of the IC development lifecycle from schematic capture and layout supervision through tape-out.
  • Silicon Validation: Partner with product and test engineering to characterize, debug, and validate first-silicon in the lab.

Required Qualifications

  • Education: Master’s or Ph.D. in Electrical Engineering or a related technical field.
  • Experience: Minimum of 7+ years of hands-on IC design experience, with a proven track record of successful production tape-outs.
  • Power Expertise: Deep technical knowledge of high-voltage gate driver architectures, level shifters, and isolation techniques.
  • Passive Modeling: Strong understanding of silicon capacitor fabrication processes, parasitic modeling, and high-frequency characterization.
  • EDA Tools: Expert proficiency with Cadence Virtuoso, Spectre, Mentor Calibre, and mixed-signal simulation methodologies.
  • Problem Solving: Exceptional laboratory debugging skills using oscilloscopes, spectrum analyzers, and high-voltage test equipment.

Preferred Qualifications

  • Experience with GaN and SiC power FET driving requirements.
  • Knowledge of advanced multi-chip module (MCM) packaging and SiP (System-in-Package) design.

We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, national origin, disability status, protected veteran status, or any other characteristic protected by law.

Skills Required

  • Master's or Ph.D. in Electrical Engineering or related technical field
  • Minimum of 7+ years hands-on IC design experience with successful production tape-outs
  • Deep knowledge of high-voltage gate driver architectures, level shifters, and isolation techniques
  • Strong understanding of silicon capacitor fabrication processes, parasitic modeling, and high-frequency characterization
  • Expert proficiency with Cadence Virtuoso, Spectre, Mentor Calibre, and mixed-signal simulation methodologies
  • Transistor-level design, simulation, and verification of complex analog and mixed-signal power blocks; tape-out ownership
  • Exceptional laboratory debugging skills using oscilloscopes, spectrum analyzers, and high-voltage test equipment
  • Experience with GaN and SiC power FET driving requirements
  • Knowledge of advanced multi-chip module (MCM) packaging and System-in-Package (SiP) design

Cree Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cree and has not been reviewed or approved by Cree.

  • Fair & Transparent Compensation Pay is often described as fair or decent in technician and operator roles. Compensation in some project management and security supervision roles is characterized as good.
  • Healthcare Strength Benefits include medical, dental, and vision coverage with HSA, FSA, and HRA options, plus EAP support. Wellness resources are highlighted alongside core health plans.
  • Parental & Family Support The package includes six weeks of paid parental leave and adoption assistance. Leave applies to new birth, adoption, and foster placement.

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The Company
HQ: Racine, WI
2,773 Employees
Year Founded: 1987

What We Do

Cree | Wolfspeed is the global leader in silicon carbide technology and production, leading the worldwide transition from silicon to silicon carbide. Our product portfolio provides disruptive technology solutions that support a more efficient, sustainable future including electric vehicles, fast charging, 5G, power supplies, renewable energy and storage, as well as aerospace and defense. Our people are dedicated to driving a significant shift in the technology sector and creating a global semiconductor powerhouse. For additional product and Company information, visit www.cree.com.

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