Design Engineering Architect - AE

Posted 14 Hours Ago
Be an Early Applicant
Cary, NC
154K-286K Annually
Expert/Leader
Cloud • Hardware • Software • Semiconductor
The Role
The Design Engineering Architect will lead the DFT team from RTL to GDSII to Silicon Debug, focusing on DFT strategies like scan chain insertion and ATPG. They will debug failures, verify testbenches, and work collaboratively with cross-functional teams, ensuring quality and thoroughness in problem solving.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for SoC/ASIC Digital Design For Test (DFT) Architect. An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

  • Prior15+ years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
  • Should be able to work as DFT Architect and Lead the DFT team from RTL to GDSII to Silicon Debug
  • Should possess intimate knowledge of DFT insertion flows
  • Basic scan chain insertion using synthesis or other software tools
  • Experience in compression scan insertion, LBIST and other scan technologies
  • Intimate knowledge of memory build-in self-test (MBIST)
  • Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
  • Debug and Analysis of failures to improve fault coverage
  • Verification of ATPG testbenches and debugging root cause of simulation mis-compares
  • Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
  • Knowledge of timing analysis and equivalency checks would be added bonus
  • Ability to work in collaborative team environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Should be able to finish DFT tasks independently
  • Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
  • Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
  • Self-driven and committed individual who can work in a fast-paced project environment

The annual salary range for San Jose, CA is $ 154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Asic
Soc
Verilog
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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