The Role
Responsible for netlist to GDS delivery, PNR and timing closure, and requiring expertise in scripting and Cadence tools.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Role : Design Engineer 1, Digital Physical Desing
- Responsibilities
- Block level Netlist to GDS delivery
- Subsystem level PnR and timing closure
- Required Skills
- 3+ years of experience in PnR and STA
- Handson experience in RTL/Netlist to GDS delivery of blocks
- Good exposure to Placement, CTS and Routing techniques
- Capable of doing PV and IREM fixes along with timing
- Good exposure to Cadence EDA tool set needed for PD
- TCL and PERL scripting knowledge and experience in writing the scripts
- Optional Skills
- Complex blocks floorplan, PnR and STA
- Complex IP integration like DDR and PCIe
- Hands on experience in low power designs
- Good understanding of DFT stitching
- Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
Top Skills
Cadence Eda Tool Set
Perl
Tcl
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The Company
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
