Design Engineer - CPU Subsystem

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San Jose, CA
In-Office
140K-210K Annually
Semiconductor
The Role

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Why Join Us?

  • Opportunity to work on cutting-edge ARM-based SoC designs.
  • Work with a team in a high-impact, fast-paced environment.
  • Competitive compensation and career growth opportunities.
  • Work alongside some of the best minds in the semiconductor industry.

What You'll Do

  • As a key member of the team, you will own the Interrupt Subsystem components for multi-core Arm based CPU SOC
  • Create Micro-Architecture documentation for the Interrupt Subsystem
  • Configure Arm GIC Interrupt controller and distributor at CPU subsystem
  • Integrate Configured RTL into subsystem and full chip level
  • Collaborate with DV Engineers and Support Debugging activities
  • RTL Quality checks using Spyglass
  • Generate UPF power definitions to support multi-power domains
  • Perform first level Synthesis to enable RTL delivery
  • Collaborate with backend team for Synthesis, implementation, STA, etc.

What You'll Need

  • We are looking for a minimum 8+ years in SoC architecture/design.
  • Proficiency with ARM-specific SoCs.
  • Strong background in digital design, RTL coding (Verilog/VHDL), and ASIC/FPGA debug methodologies
  • Proven experience in SOC design
  • Strong knowledge of interrupt distribution within multi-core CPU SoC and across Chiplets
  • Deep understanding of hardware design, verification, and post-silicon validation

It Would Be Amazing If You Had

  • Experience in multi-core, multi-voltage, multi-power domain debug design micro-architecture and RTL design
  • Supporting and bringing up FPGA, Emulation based systems
  • Experience working across multiple chiplets in large-scale SOCs
  • Hands-on SoC bring up experience in a lab environment

We have a flexible work environment to support and help employees thrive in personal and professional capacities.

Salary and Benefits

Your contribution will be recognized with a base salary within the range of $140,000 to $210,000 annually as It is influenced by your qualifications, experience, location, and the internal equity of our team to ensure fairness and consistency across roles. In addition to our comprehensive benefits package, employees are also eligible for additional compensation opportunities, including a short-term incentive program, Retirement & Saving Programs and participation in the Employee Stock Purchase Plan (ESPP)

You'll also be eligible for competitive benefits described as per below:

Health & Wellness

Our programs emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.

  • Comprehensive health plans
  • Wellness Spending Account (WSA)
  • Employee Assistance Program (EAP)

Time Off

We value the importance of rest and recharge, which is why we offer flexible time off options to support your well-being.

  • Paid Vacation
  • Paid Holidays
  • Parental Leave

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

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The Company
HQ: Toronto, Ontario
636 Employees
Year Founded: 2017

What We Do

We work to create silicon that enables the highest performing, most reliability and lowest power digital communication networks.

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