Cadence HSV group is responsible for development of the Palladium and Protium emulation hardware and software system. This includes developing design and verification components for complex protocols, to be used for emulation, for e.g. System Verilog/Verilog components and SW components written in C/C++ and SV-UVM. It also requires development of system level RTL methodologies for stitching together large complex RTL designs in a scalable and reusable manner using and developing advanced tools including those that use AI and ML techniques.
A critical element with building these SoC models is performance, encompassing performance of the AVIP, the underlying hardware-software design/integration, the compiler and the processor-based Palladium emulator hardware system.
Job Description:
We are seeking a skilled HW and/or Design Engineering Architect to lead building representative SoC sub-systems using partner systems (ARM, others) and Cadence design and verification collateral. The main task is to build ARM CSS based systems using Cadence AVIPS and IP, port these to Palladium/Protium hardware and software and ensure functional correctness and make recommendations for performance improvements. Experience with SoC design, verification, ARM bus protocols and performance analysis is required. Familiarity with or interest in developing new methodologies for SoC Integration and Verification Automation is a plus.
Skills needed:
15-18 years of hands-on HW RTL development and verification experience
Emulation experience on Palladium/Protium
Expertise in AMBA and CHI protocols
Knowledge with design/integration of SoC systems
Experience with performance analysis of complex hardware-software systems.
Familiarity with standard communication protocols PCIe, CXL is a plus
Good communication skills, excellent inter-personal skills, motivated individual
Ability to analyze and propose solutions to complex problems.
Skills Required
- 15–18 years of hands-on hardware RTL development and verification experience
- Experience with Palladium or Protium emulation
- Expertise in AMBA and CHI protocols
- Knowledge of SoC system design and integration
- Experience analyzing performance in complex hardware-software systems
- Ability to analyze complex problems and propose solutions
- Strong communication and interpersonal skills
- Familiarity with PCIe and CXL communication protocols
- Interest in or familiarity with SoC integration and verification automation methodologies
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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