CXLCM micro-Architect/Senior Logic Design Engineer

Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, come join us to do something wonderful. The IP Engineering Group is looking for energetic and passionate senior Design leaders to work closely with established ASIC design team for advanced digital IO controller (like PCIe, UPI, CXL, IOMMU etc.) IP implementation on cutting edge technology nodes.

Who You Are

Your responsibilities include but are not limited to:

• Oversee definition, architecture design, and documentation for SoC development.

• Work on micro-architecture design, logic design, and system simulation.

• You will perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing, and power to create a design database that is ready for SoC integration.

• Mentoring and coaching junior verification engineers.

• Leadership to manage stakeholders with end-to-end objectives in mind.

• The candidate should have the ability to work effectively with both internal and external teams/stakeholders.

• Should possess strong problem solving/communication skills. Should be a very good team player.

• Works closely with established ASIC design team on IP implementation for advanced high-speed controller with chip-to-chip communication between CPU, memory and accelerator on cutting edge technology node.

• Oversees definition, design, verification, and documentation for SoC System on a Chip development.

• Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.

• Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.

• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.

• Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications

• Bachelor’s Degree in Electrical Engineering with 6 years of experience in Digital Logic Design or Master’s Degree in Electrical Engineering with 4 years of experience in Digital Logic Design.

Preferred Qualifications

• Bachelor’s Degree in Electrical Engineering with 7 years of experience in Digital Logic Design or Master’s Degree with 5 years of experience in digital logic design.

• Direct experience with Micro-Architecture, integrating IPs and cross-functioning with IP teams.

• Strong understanding of hardware design, design verification, timing analysis, clock domain crossing, and lint.

• Proficient in Synthesis and Timing Closure.

• Experience with Design Compiler and PrimeTime.

• Comfortable with scripting languages such as Perl, Tcl, etc.

• Experience with Design for Test and Design for Debug methodologies

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Oregon, Hillsboro

Business group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.