CPU Memory Systems RTL Lead

CPU Memory Systems RTL Lead will drive the development of Tenstorrent’s next-generation CPU RTL. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the team building, the microarchitecture specification, RTL design, and verification.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

•  Define and develop microarchitecture specifications for CPU (loadstore, data prefetch, cache coherency protocol, shared cache, etc…). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.
• Define and develop interface between CPU core and external memory subsystem. This drives the definition of bus interface protocol including cache coherence protocol.
• The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.
• To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.

Experience & Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven track record of memsys RTL design (e.g., loadstore) for high-performance CPU.
• Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…). The candidate should understand how to verify if your design complies with certain memory ordering rules.
• Deep understanding of CPU microarchitecture and PPA trade-off.
• Deep understanding of memory ordering model.
• Basic understanding of AMBA CHI protocol is preferred.
• Basic understanding of RISC-V Architecture is preferred.
• Proficiency in hardware description languages (HDLs) such as Verilog or VHDL.
• Excellent problem-solving abilities and analytical skills.
• Strong communication skills, with the ability to convey complex technical concepts to diverse audiences.
• Ability to work collaboratively in a team-oriented environment and across multiple disciplines.
  

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.