CPU Core Logic Designer

Job Details:

Job Description: 

As a CPU Core Logic Designer responsibilities will include but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
• Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Documents micro architectural specs (MAS) of the CPU features being designed.
• Supports SoC customers to ensure high-quality integration of the CPU block.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering or Computer Science and 8+ years of experience or a Master's degree in Electrical/Computer Engineering or Computer Science and 6+ years of experience.
• 6+ combined experience in:
  • System Verilog/Verilog/VHDL and/or VCS or similar Simulator
  • Logic design and/or front end.
  • Computer architecture and microarchitecture.
  • Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.).
  • Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization.

Preferred Qualifications:

• Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high speed circuit design and optimization for Datapath, circuits and/or arrays.
• Familiarity with circuit planning and timing convergence.
• Experience working with cross functional teams (Architecture, Spec development, Design, Formal, Verification).

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.  

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:

Business group:The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.