The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a CPU Memory Design Engineer. In this role, you will be responsible for designing, developing, and building full-custom as well as compiler-based SRAMs, Large Signal Arrays (custom multi-ported register file), ROMs, custom memories, digital circuits and Caches for Intel CPU and SOCs. You will be partnering with and leveraging domain experts across various areas of technology development to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on advanced CMOS process technologies for Intel CPU and SOCs.This will be a fast-paced dynamic environment where you will work in the high performance, low power CPU design team on a wide spectrum of circuit activities including, but may not be limited to:- Technical readiness, memory circuit design, characterization and simulations.- Cache design, critical path simulations and design custom blocks to meet stringent Power/Performance/Area constraints.- Memory path-finding activities and power, performance and area (PPA) optimization.- Memory bit-cell and complex periphery IC design and automation.- Memory array/IP design, memory circuit innovation- Methodology definition tasks as well as executing project schedules.
- Proficiency in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area.
- Expertise in Very Large Scale Integration (VLSI) circuits and design methodologies.
Qualifications
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with 6+ years of experience;
- Or Master's degree with 5+ years of experience;
- Or PhD with 2+ years of experience.
Preferred Qualifications:
- Experience in low-power implementation techniques and memory design.
- Familiarity with circuit and layout trade-offs for optimized design.
- Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
- Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments.
Help shape the future of technology and join a team that's driving innovation at the forefront of CPU design. Apply now to make a meaningful impact at Intel.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM with 6+ years experience OR Master's with 5+ years OR PhD with 2+ years.
- Proficiency in CMOS circuit design, digital logic optimization, and PPA (power, performance, area) trade-offs.
- Expertise in VLSI circuits and design methodologies.
- Experience designing/developing SRAMs, ROMs, custom memories, register files, memory arrays, and caches.
- Experience with memory circuit characterization and simulation.
- Ability to consent to and pass an extended background investigation (Position of Trust).
- Experience in low-power implementation techniques and memory design.
- Familiarity with circuit and layout trade-offs for optimized design.
- Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
- Strong analytical and problem-solving skills, ability to prioritize tasks in dynamic environments.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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