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The Role
Lead design analysis and methodology for memory blocks and datapath subsystems for high-speed, low-power CPUs. Enable memory methodologies to meet >5GHz, work with layout/floorplanning, implement back-end features, perform memory post-silicon analysis, and apply static timing and statistical variation expertise.
Summary Generated by Built In
Job Details:Job Description: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:
1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).
3. Expertise in Static timing analysis concepts.
4. Close work with Layout and Floor planning teams.
5. Back-end design implementation of new features.
6. Expertise in Memory post silicon analysis.
7. Good understanding of statistical variation.Qualifications:You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.
Preferred Qualifications:
1. Digital Design Experience, with High Speed, Low Power.
2. Familiarity with Verilog.
3. Tcl, Perl, Python scripting.
4. Good understanding of spice simulations and analysis
5. Strong verbal and written communication skills.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Masters Degree in Electrical or Computer Engineering with at least 8 years experience, or Bachelors with at least 10 years
- Expertise in Static Timing Analysis concepts
- In-depth understanding of memory design concepts (SRAM/RF/ROM)
- Expertise in memory post-silicon analysis
- Good understanding of statistical variation
- Technical expertise in synthesis
- Experience with P and R (place-and-route) tools
- Digital design experience (high-speed, low-power)
- Familiarity with Verilog
- Tcl, Perl, Python scripting experience
- Good understanding of SPICE simulations and analysis
- Strong verbal and written communication skills
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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