We are excited to welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance Solutions Group (PSG). Working at Cadence means collaborating with some of the industry’s brightest minds and driving innovation for the world’s most advanced companies. Through Cadence’s tools, emulation hardware, and IP products, we have supported a diverse range of customers. Enabling products in data centers, advanced driver-assistance system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence verticals.
As an expert Physical Design Architect, you will engage directly with our leading-edge customers to deliver differentiated RTL-to-GDS services in advanced FinFET nodes. You will lead a talented Physical Design team with the goal of not only meeting but exceeding customers’ demanding Performance, Power, Area, and Schedule (PPAS) targets. At Cadence, our customers are at the heart of everything we do, and talented leaders like you are essential to turning this passion into tangible results.
Key Responsibilities- Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs are targeted for markets such as data centers, automotive, and artificial intelligence.
- Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements.
- Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs.
- Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency.
- Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate.
- Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements.
- Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs
- Fifteen or more years of industry experience in Physical Design.
- Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
- Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
- Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
- Demonstrated experience in complete design closure for chip top-level projects.
- Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
- Experience with advanced nodes at 7nm and below.
- Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
- Strong customer-facing communication and problem-solving skills.
- Personal drive for continuous learning and expanding professional skill sets.
- Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.
- Master’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
- Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
- Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or with similar tools like ICC, ICC2, DC, or Primetime is highly desired.
- Experience with advanced nodes at 5nm and below.
- Domain expertise in CPUs, GPUs, AI Engines, Networks on Chip (NoCs), or high-speed interfaces.
- Experience with 3D IC design is a significant plus.
Skills Required
- Fifteen or more years of industry experience in physical design
- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
- Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis, including timing constraints
- Experience with IC digital implementation flows and backend EDA tools, including place and route, clock tree synthesis, IR drop analysis, backend timing, and power closure
- Demonstrated experience achieving complete design closure for chip top-level projects
- Expertise in PPA optimization and performance, power, and area trade-offs
- Experience with advanced semiconductor nodes at 7nm and below
- Proficiency in Tcl, Perl, or Python scripting
- Strong customer-facing communication and problem-solving skills
- Ability to build technical relationships with RTL, DFT, CAD, and library teams
- Personal drive for continuous learning and expanding professional skills
- Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
- Experience with synthesis, DFT, and logical equivalence checking
- Experience with Cadence Genus, Innovus, Conformal, Tempus, Modus, Voltus, or comparable tools such as ICC, ICC2, Design Compiler, or PrimeTime
- Experience with advanced semiconductor nodes at 5nm and below
- Domain expertise in CPUs, GPUs, AI engines, Networks on Chip, or high-speed interfaces
- Experience with 3D IC design
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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