Associate Staff Engineer- DFT (Wireless SoC) 8+yrs of experience - HYDERABAD

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance

Responsibilities:

Candidate will be responsible for driving DFT implementation in Wireless SoC chips. The person will have full ownership of ATPG architecture, design, implementation, verification and deployment to Silicon testing, working with Test engineer. The responsibilities also include MBIST design, implementation and verification for all memories in the SoC. Person should be capable of generate and debug DFT patterns on tester. Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow.

Skills you'll need

• 8 to 10yrs of Full-chip DFT working experience with multiple design Tape Outs
• Expert knowledge of DFT architecture on complex Design with multiple clock domains.
• Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults .
• Hands-on experience in industry standard DFT tools - Mentor Tessent suite or Synopsys DFT compiler.
• Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
• Expertise in Scan Compression(EDT/OPMISR+), MBIST, ATPG implementation and verification.
• Expert knowledge on Test time reduction.
• Good Knowledge of cross functional domains (SYN, LEC, STA, PD) with owner ship of constraints developments & LEC.
• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
• Experience working with cross functional global teams
• Experience in Low-Power DFT requirements.
• Experience in Low-Power MBIST architectures and Memory testing.
• B.Tech/M.Tech in ECE, EEE

Preferred skills:

• Experience in DFT related RTL integration.
• Excellent communication and analytical skills
• Experience in leading junior teams, Mentoring/Training and Project leadership.
• Exceptional problem-solving skills

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.