ASIC/SOC Silicon Physical Design Engineer

Posted 5 Days Ago
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Mountain View, CA
Senior level
Artificial Intelligence • Hardware • Software
The Role
Silicon Physical Design Engineers at MatX develop high-performance silicon for various products, overseeing the entire Physical Design process from RTL to GDSII. Responsibilities include contributing to design methodology, managing chip-level deliverables, and collaborating with design and verification teams to achieve optimal performance, power, and area results.
Summary Generated by Built In

MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes.

Responsibilities include:

  • Contribute to MatX’s Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII
  • Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification)
  • Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout
  • Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results

Requirements:

  • Bachelor of Science in Electrical Engineering or equivalent
  • Minimum 8 years of industry experience in ASIC Physical Design
  • Great interpersonal and communication skills
  • Strong proficiency in programming languages such as Perl, Python, and TCL
  • Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL to production silicon
  • Experience collaborating with Design, Verification, and DFT teams to structure, partition, and optimize designs for PPA through sign-off

Preferred Experience:

  • 8 years of industry experience in ASIC Physical Design
  • Experience working with third-party Design Services partners

Compensation: The US base salary for this full-time position is $120,000 - $400,000 + equity + benefits

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

Top Skills

Perl
Python
Tcl
The Company
HQ: Mountain View, CA
19 Employees
On-site Workplace

What We Do

MatX designs hardware tailored for the world’s best AI models: We dedicate every transistor to maximizing performance for large models. For these models, we deliver 10× more computing power, enabling AI labs to make models an order of magnitude smarter and more useful. Our hardware would make it possible to train GPT-4 and run ChatGPT, but on the budget of a small startup.

A world with more widely available intelligence is a happier and more prosperous world—picture people of all socioeconomic levels having access to an AI staff of specialist MDs, tutors, coaches, advisors, and assistants.

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