ASIC Verification - Technical Lead/Manager

Posted 11 Days Ago
Be an Early Applicant
3 Locations
In-Office
Expert/Leader
Hardware • Information Technology • Software
The Role
The ASIC Verification Lead will develop verification strategies, implement test plans, oversee test environments, and mentor junior engineers to ensure the functional correctness and performance of AI ASICs.
Summary Generated by Built In

Positron.ai specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.


Position Overview:

As the ASIC Verification Lead, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for developing and executing advanced verification methodologies, working closely with design, architecture, and software teams to validate our silicon solutions. This is an opportunity to lead a talented team and contribute to the evolution of AI hardware technology.

Key Responsibilities:
  • Develop and execute verification strategies for AI inference ASICs.
  • Define and implement comprehensive test plans and verification methodologies.
  • Lead the development of verification environments using SystemVerilog/CocoTB.
  • Create and maintain simulation testbenches, directed and constrained-random tests.
  • Collaborate with design and architecture teams to ensure functional coverage and closure.
  • Drive debugging and root cause analysis of design issues in pre-silicon and post-silicon validation.
  • Work with FPGA and emulation teams for early hardware validation.
  • Manage verification schedules, deliverables, and risk mitigation plans.
  • Mentor and guide junior verification engineers in best practices and methodologies.
Required Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC verification, including leadership roles.
  • Expertise in SystemVerilog, CocoTB methodology, and simulation tools.
  • Strong knowledge of verification planning, testbench development, and coverage-driven verification.
  • Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics).
  • Hands-on experience with debugging tools, waveform analysis, and scripting (Python, Perl, or TCL).
  • Familiarity with AI/ML accelerators, memory subsystems, and high-speed interconnects.
  • Proven track record of successfully verifying complex ASIC designs.
Preferred Qualifications:
  • Advanced degree in Electrical or Computer Engineering or related field.
  • Experience with hardware-software co-verification.
  • Knowledge of formal verification techniques.
  • Understanding of post-silicon validation and bring-up methodologies.
Why Join Positron.ai?
  • Be part of a rapidly growing AI startup shaping the future of AI hardware.
  • Work on groundbreaking technology with a highly skilled and passionate team.
  • Competitive salary, equity, and comprehensive benefits package.
  • Flexible work environment with remote work options.

If you are excited about ensuring the highest quality AI hardware and leading an advanced verification team, we want to hear from you! Apply today.


Top Skills

Cadence
Cocotb
Mentor Graphics
Perl
Python
Synopsys
Systemverilog
Tcl
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The Company
HQ: Reno, NV
42 Employees
Year Founded: 2023

What We Do

Positron delivers vendor freedom and faster inference for both enterprises and research teams, by allowing them to use hardware and software explicitly designed from the ground up for generative and large language models (LLMs).

Through lower power usage and drastically lower total cost of ownership (TCO), Positron enables you to run popular open source LLMs to serve multiple users at high token rates and long context lengths. Positron is also designing its own ASIC to expand from inference and fine tuning to also support training and other parallel compute workloads.

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