About Tensordyne
AI is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different modalities and environments - with the ability to quickly learn and then solve complex problems. Tensordyne is an AI system solution company that builds very high-performance, low-power generative AI inference systems. Our mission, through the creation of custom silicon, hardware and software, is to enable multimodal Generative AI inference acceleration at scale, with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers. We are at the leading edge of advancing the latest research and product improvements for generative Al inference solutions that will make Al even more advantageous for compelling new generative AI applications.Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely across North America and Europe. We take care of our people and their families with comprehensive benefits, competitive compensation, flexible spending options, and recognition programs, because building category-defining technology starts with a healthy, supported team. Come join us as we shape the future of multimodal generative artificial intelligence!
As a member of Tensordyne's ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record- breaking computational performance at low power.
- Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.
- SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)
- Develop the block-level, sub-system and full-chip verification environment and tests to implement test plans.
- Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.
- Triage and debug functional and performance issues with the design-under-test.
- Handle bug tracking and coverage convergence.
- Perform diagnostic and post-silicon validation tests in the lab.
Required Qualifications:
- 2+ years of ASIC verification experience.
- Knowledge of ARM/MIPS/RISC-V Architecture
- Familiarity with AMBA/APB/AXI Protocol
- Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
- Excellent Verilog/System Verilog programming skills.
- Experience with UVM (or similar).
- Deep understanding of object oriented programming principles, constrained random stimulus, and a coverage driven verification approach.
- Scripting experience (Python, Perl, TCL, shell programming) highly-desirable.
- Interest to explore AI architectures for convolution, transformer and other kinds of workloads
- Self-starter and highly-motivated to work in a dynamic start-up environment.
- B.S. (M.S. preferred) degree in Electrical or Computer engineering (or similar field).
- Put people first. We only succeed when our people succeed.
- Ethics and integrity always; Being open, honest, and respectful of everyone.
- Think Big. Be ambitious and have audacious goals.
- Aim for excellence. Quality and excellence count in everything we do.
- Own it and get it done. Results matter!
- Make Each Person Better together than they would be as an individual.
- Embrace each others’ differences.
- Embrace that there will be differences.
Recogni is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
A note to Recruitment Agencies: Please don’t reach out to Recogni employees or leaders about our roles -- we’ve got it covered. We don’t accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.
Skills Required
- 2+ years of ASIC verification experience
- Knowledge of ARM/MIPS/RISC-V Architecture
- Familiarity with AMBA/APB/AXI Protocol
- Excellent Verilog/System Verilog programming skills
- Experience with UVM or similar verification methodologies
- Scripting experience (Python, Perl, TCL, shell programming) highly-desirable
- B.S. (M.S. preferred) degree in Electrical or Computer engineering (or similar field)
What We Do
Every leap in AI has followed the same pattern: first we made models bigger, then we tailored them, and now we let them think longer. Each step (scaling law) truly adds intelligence. But in the end we land on the same runway: inference, and demand is exploding while power supply lags. We asked: what if the next step isn’t stacking another law on top, but a zeroth law beneath them all. A law that changes AI math. Because after all, AI is math, trillions of multiplies, and multiplication burns watts. Tensordyne uses logarithmic compute to turn multiplies into adds, cutting power at the root. We’ve cast our proprietary logarithmic math into custom silicon, hardware, interconnect, and system software. The result: one integrated system for multimodal GenAI inference designed for Hyperscaler and Neo Cloud data centers. What this means for our customers: With Tensordyne they can run the world’s largest multimodal models for thousands of users, with fewer racks, less power, and lower cost. We’re well-funded and fast-moving, with co-headquarters in Sunnyvale, California and Munich, Germany, and a distributed team across North America and Europe. Join us to change how the world runs Gen AI.
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