ASIC Tech Lead (Analog)

Lumai is redefining how the world computes. We are an ambitious, venture-backed UK startup pioneering a breakthrough AI accelerator for data centers which uses 3D optical compute. Our radical technology uses light to perform computation at orders of magnitude faster speeds and at far greater scales than ever before, all whilst consuming far less energy than traditional approaches.

Lumai is unlocking performance and efficiency gains that could transform the economics of AI and compute infrastructure and reshape how intelligence scales globally.

If you are passionate about bringing groundbreaking technology to market, and want to be part of a team pushing the boundaries of what is physically possible, Lumai is where you can make it happen.

Founded in 2022, Lumai is a University of Oxford spinout using optical processing to accelerate large language models (LLMs) and other transformer-based AI systems. The team combines expertise in optical computing, machine learning, and physics.

Lumai has already secured over $15 million in investment from leading deep-tech investors like Constructor Capital, IP Group, PhotonVentures and government grants, and is scaling rapidly to deploy the fastest optical compute currently available globally.

Lumai is developing a photonic AI compute chip that processes data using light rather than electrons — an architecture that demands world-class analog and mixed-signal design at its core. The photodetectors, transimpedance amplifiers, variable-gain amplifiers, high-speed ADCs, and analog control loops that sit at the interface between our photonic and digital domains are not commodity IP: they define the performance envelope of our entire platform.

As our ASIC Tech Lead (Analog), you will own the analog and mixed-signal subsystems end to end — from architecture and specification through schematic capture, layout review, simulation sign-off, silicon bring-up, and characterisation. You will set the technical direction for analog design at Lumai, define our circuit methodologies and design flows, and be the go-to authority on everything from low-noise front-ends to high-speed interfaces and precision bias generation.

This is a hands-on senior individual contributor role with strong technical leadership responsibility. You will mentor junior designers, collaborate closely with our photonics, digital ASIC, and firmware teams, and work directly with our foundry partners and EDA toolchain providers. You report to the Head of Engineering.

• Architect and own Lumai’s analog and mixed-signal subsystems, including TIA front-ends, VGAs, high-speed ADCs/DACs, PLLs, LDOs, bandgap references, and on-chip bias/calibration circuits

• Lead circuit design from concept through full custom schematic capture, pre- and post-layout simulation, and sign-off — taking personal ownership of critical blocks

• Define and enforce analog design methodologies, simulation corner strategies, and layout guidelines (matching, shielding, guard rings, substrate noise isolation) across the team

• Drive the analog/mixed-signal portions of tapeout: own the sign-off checklist, review LVS/DRC results, and coordinate with the digital and layout teams to meet tape-out milestones

• Lead silicon bring-up and characterisation of analog blocks — define bench test plans, debug first-silicon issues, and close the loop between measured silicon behaviour and simulation models

• Collaborate with the photonics team to define electrical interfaces to photonic devices (photodetectors, modulators) and co-optimise for noise, bandwidth, and power

• Work with the digital ASIC and firmware teams to specify ADC/DAC interfaces, calibration sequences, and real-time closed-loop control requirements

• Evaluate and manage the EDA toolchain for analog design (Cadence Virtuoso, Spectre, Calibre, etc.) and maintain or extend the PDK/IP library

• Mentor and technically grow junior and mid-level analog designers; conduct design reviews and set the bar for simulation rigour and documentation quality

• Engage directly with GlobalFoundries (or other foundry partners) on PDK questions, process corners, and device modelling queries related to 22FDX or equivalent process nodes

Must-Have

• 8+ years of hands-on analog or mixed-signal ASIC design experience, with at least one tapeout in a production-intent or high-volume context as the lead designer on one or more critical blocks

• Deep expertise in one or more of: TIA/VGA design for optical receivers, high-speed ADC/DAC architectures (SAR, pipeline, sigma-delta), PLL/clock generation, or precision analog (bandgap, LDO, bias)

• Strong command of full-custom design flow: schematic, transistor-level simulation (Spectre or similar), post-layout extraction, and statistical/Monte Carlo sign-off

• Hands-on silicon bring-up and characterisation experience — comfortable at a bench with an oscilloscope, VNA, signal analyser, and custom test fixtures

• Working knowledge of advanced CMOS process nodes (28nm and below, including FD-SOI or FinFET); familiarity with device physics and its practical impact on analog performance

• Experience with physical design constraints for analog: matching strategies, layout-dependent effects, shielding, electromigration, and ESD structures

• Ability to communicate across disciplines — translating analog constraints and trade-offs clearly for digital designers, firmware engineers, and product stakeholders

• MSc or PhD in Electrical Engineering, Microelectronics, or a closely related field; or equivalent demonstrated expertise through industry track record

Strong Preference For

• Experience with GlobalFoundries 22FDX (22nm FD-SOI) or comparable RF/analog-optimised process nodes, including body-bias techniques for low-power or high-performance tuning

• Background in analog front-ends for photonic or optical systems — coherent or direct-detect receiver design, silicon photonics integration, or lidar/sensing front-ends

• Familiarity with mixed-signal design challenges in AI inference hardware: high-throughput data conversion, in-memory compute interfaces, or neuromorphic circuit concepts

• Experience with RFIC or mmWave design, particularly high-frequency parasitics management and EM simulation (Momentum, EMX, Sonnet)

• Prior experience at a fabless startup or research spin-out from the first tapeout through to product qualification

• Contributions to published research or patents in analog/mixed-signal IC design

• Familiarity with Python-based characterisation and data analysis workflows for silicon validation (e.g. bench automation, corner sweeps, yield analysis)

• Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress

• Share Option Scheme: We are all in this together! We believe in shared success while we build the Lumai of tomorrow

• L&D Allowance: Stay at the forefront of your field with a €500 annual development budget

• Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year

• Socials: Be part of an inclusive community enjoying occasional all-company off-sites, lunches and socials

Our process is four stages. An initial conversation with our HR team to understand what you want from the role and what we want from it. Two technical sessions with various members of our engineering team. Finally, an HR-team session covering scope, terms, and any final questions. We aim to move fast on candidates we are excited about; expect roughly three to four weeks end to end.

Lumai is an equal opportunity employer. We make hiring decisions on merit, scope-fit, and the strength of the working relationship we expect to build with each hire. Applications welcome from candidates of any background. If you are not sure whether you are a fit, send a note anyway.