ASIC RTL Design Engineer

Job Title: ASIC RTL Design Engineer

Position Type: Full-time

Location: Fremont, CA, United States

Salary Range / Rate (Currency): $110,000 - $300,000 (USD)

Job ID#: #136686

Job Summary:

We are seeking an experienced and innovative ASIC RTL Design Engineer to join our dynamic team. In this role, you will be responsible for the design, development, and testing of complex integrated circuits. This position requires a solid understanding of engineering principles and the ability to work collaboratively in a fast-paced environment. As an ASIC RTL Design Engineer, you will play a crucial role in advancing projects from concept to completion while ensuring high-quality standards and adherence to project timelines.

Essential Functions:

• Lead Register Transfer Level (RTL) design, simulation, and verification for Application-Specific Integrated Circuit (ASIC) and System-on-Chip (SoC) products.

• Integrate and validate Intellectual Property (IP) blocks to ensure functionality and compatibility within the broader system.

• Conduct Power, Performance, and Area (PPA) analysis to optimize design trade-offs and meet both internal and external requirements.

• Collaborate with the backend team in RTL coding, implementation, and synthesis, supporting successful tapeout.

• Develop and maintain reusable internal IPs with a focus on artificial intelligence (AI) and in-memory computing applications.

• Provide support for post-silicon testing and validation, addressing issues to confirm overall functionality and quality.

• Mentor junior engineers, sharing expertise and best practices to support team development.

• Participate in design reviews and cross-functional discussions, offering insights to enhance product performance and reliability.

• Stay updated on advancements in RTL design and integrate innovative techniques to improve product quality and efficiency.

• Work closely with cross-functional teams, including software, architecture, and verification, to drive cohesive product development and delivery.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering or a related field.

• 5+ years of experience in analog or mixed-signal IC development, particularly in advanced CMOS processes with successful tape-out experience.

• Proficiency in Verilog and System Verilog.

• Experience with tools such as Verification Compiler Simulator (VCS), Verdi, and familiarity with pre-layout and post-layout simulation.

• Strong understanding of AMBA APB and AXI protocols and RISC/ARM core architectures.

• Ability to create innovative architectures and solutions tailored to client requirements.

• Strong problem-solving skills, attention to detail, and ability to collaborate effectively within a team.

Preferred Qualifications:

• Experience in Field Programmable Gate Array (FPGA)/ASIC design, particularly in image processing systems.

• Familiarity with System-on-Chip (SoC) architectures, including CPU, GPU, or accelerators.

• Knowledge of Universal Verification Methodology (UVM), place-and-route processes, Static Timing Analysis (STA), Electromigration/IR drop/Power analysis.

About Us:

Founded in 2009, IntelliPro is a global leader in talent acquisition and HR solutions. We are committed to delivering unparalleled service to clients, fostering employee growth, and building enduring partnerships. With a dynamic presence in the USA, China, Canada, Singapore, Philippines, UK, India, Netherlands, and Germany, we continue leading global talent solutions.

As an Equal Opportunity Employer, IntelliPro values diversity and does not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, genetic information, disability, or any other legally protected group status. Our Inclusivity Commitment emphasizes embracing candidates of all abilities and ensures that our hiring and interview processes accommodate the needs of all applicants. Learn more about our commitment to diversity and inclusivity at IntelliPro.