Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
As a Physical Design Engineer, you will help implement Positron's AI accelerators from floorplanning through tapeout. Working under the guidance of senior engineers, you will take ownership of well-scoped blocks, run and debug implementation flows, and build hands-on experience across the full physical design cycle. You'll collaborate with RTL, synthesis, DFT, package, and backend design services teams to help achieve world-class PPA.
Key ResponsibilitiesBlock-Level Physical Implementation
- Implement assigned blocks through floorplanning, macro placement, and power planning, with guidance from senior engineers.
- Run clock tree synthesis, place and route, and routing optimization, and work toward timing closure on your blocks.
- Support signal integrity, IR/EM analysis, ECO implementation, and metal fill to help deliver signoff-quality results.
- Contribute to tapeout signoff activities for your blocks.
Methodology & Flow Support
- Help maintain and improve flows for power grids, power/ground tiles, and bump planning.
- Run congestion analysis and wire estimation to support floorplan decisions.
- Learn and apply hierarchical implementation and partitioning strategies on multi-block designs.
Tools & Automation
- Run and debug Innovus-based implementation flows.
- Build hands-on experience with tools such as Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre.
- Write Tcl and Python scripts to automate tasks, parse reports, and improve team productivity.
Closure & Signoff
- Analyze and fix issues across timing, power, area, congestion, DRC, LVS, EM, and IR for your blocks.
Collaboration & Reviews
- Work with backend design services partners on block-level execution.
- Take part in implementation reviews, present your results, and incorporate feedback.
AI-Enabled Engineering
- Use AI-enabled tools to support QoR analysis, congestion prediction, routing prediction, and floorplan optimization.
- BS/MS in EE/CE (or related field) with 0–8 years of physical design experience (internships and relevant graduate research count).
- Understanding of the physical design flow, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Working knowledge of static timing analysis concepts (setup/hold, clock skew, timing constraints).
- Exposure to at least one major implementation tool (Innovus, ICC2, or equivalent) from industry or academic projects.
- Familiarity with physical verification concepts such as DRC and LVS.
- Scripting ability in Tcl, Python, or similar.
- Strong problem-solving skills, eagerness to learn, and clear communication.
- Experience on an advanced-node or academic tapeout.
- Exposure to IR drop, EM, or signal integrity analysis.
- Coursework or project experience in VLSI design, computer architecture, or AI accelerators.
- Familiarity with large SRAM arrays, SerDes, or LPDDR interfaces.
- Interest in chiplet architectures and 2.5D advanced packaging.
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a different level for the right candidate. This job description is a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience of the final hire.
What Success Looks LikeWithin one year, this person will have taken one or more blocks through implementation with clean timing and signoff results, become proficient in our implementation flows and tools, contributed useful scripts or flow improvements to the team, and grown toward independent block ownership.
Why Join Us?- Help build physical implementation for a new class of AI inference accelerators from the ground up.
- Work at the cutting edge of advanced-node design, learning to tackle hard problems in power, timing, and signal integrity for frontier AI workloads.
- Learn directly from experienced physical design engineers, with real block ownership early in your career.
The base salary range for this role is $150,000 – $200,000.
These figures represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.
Benefits & PerksWe want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
Health and wellness
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
Time off and flexibility
- Unlimited paid time off, so you can truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
Compensation and future
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.
Skills Required
- 12+ years of experience in physical design (floorplanning through tapeout).
- Proven track record across multiple advanced-node tapeouts.
- Expert-level proficiency in Innovus and ICC2 implementation flows.
- Hands-on expertise with Tempus, PrimeTime, Voltus, RedHawk, and Calibre.
- Deep expertise in physical implementation including floorplanning, clock tree synthesis, timing and power closure.
- Experience driving full signoff across timing, power, DRC/LVS, EM/IR, and yield.
- Authorized to work in the U.S.; employer cannot provide new visa sponsorship (H-1B transfers may be facilitated).
- Experience with AI accelerator design.
- Familiarity with large SRAM arrays.
- Experience with SerDes and LPDDR interfaces.
- Exposure to chiplet architectures and 2.5D advanced packaging.
What We Do
Positron delivers vendor freedom and faster inference for both enterprises and research teams, by allowing them to use hardware and software explicitly designed from the ground up for generative and large language models (LLMs). Through lower power usage and drastically lower total cost of ownership (TCO), Positron enables you to run popular open source LLMs to serve multiple users at high token rates and long context lengths. Positron is also designing its own ASIC to expand from inference and fine tuning to also support training and other parallel compute workloads.
