Asic Design Verification Engineer

Posted 19 Days Ago
Be an Early Applicant
United States of America
119K-190K Annually
7+ Years Experience
Semiconductor
The Role
The ASIC Design Verification Engineer will contribute to the development of complex SOCs and be responsible for architecting verification environments, developing test plans, debugging simulations, writing diagnostics, and automating verification flows. Requires BS with 8+ years of experience or MS with 6+ years of experience in Electrical Engineering or Computer Engineering.
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Job Description:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:


○ Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
○ Develop test plans and coverage metrics from specifications and write block and chip-level tests.
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environment and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.

○ Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.
○Knowledge of mixed-signal simulations (AMS, Spice) etc.

 

Minimum Job Requirements:

○ Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
○ Develop test plans and coverage metrics from specifications and write block and chip-level tests.
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.

Experience : BS and 8+ years of related experience in Electrical Engineering or Computer Engineering; or MS and 6+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $119,000 - $190,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Top Skills

Verilog
The Company
HQ: San Jose, CA
38,985 Employees
On-site Workplace
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs,
develops and supplies semiconductor and infrastructure software solutions.

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