ASIC Design Lead/Manager

Posted 5 Days Ago
Be an Early Applicant
3 Locations
In-Office
Expert/Leader
Hardware • Information Technology • Software
The Role
Lead ASIC design for AI inference chips, collaborating with teams on architecture, validation, and design methodologies. Mentor ASIC designers and drive product innovation.
Summary Generated by Built In

Positron.ai specializes in developing custom hardware systems to accelerate AI inference.  These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt.  Positron exists to create the world's best AI inference systems.


Position Overview:

As the ASIC Design Lead, you will be responsible for leading the architecture, design, and implementation of our AI inference chips. You will work closely with cross-functional teams, including software, verification, and system architects, to deliver high-performance, low-power AI accelerators. This is a key leadership role where you will influence the company’s ASIC roadmap and product innovation.

Key Responsibilities:
  • Lead the architecture and design of ASIC solutions for AI inference workloads.
  • Define microarchitecture, develop RTL design, and drive implementation from concept to silicon.
  • Work closely with verification and validation teams to ensure robust functional correctness.
  • Collaborate with physical design teams to optimize for power, performance, and area (PPA).
  • Define and drive design methodologies, best practices, and process improvements.
  • Interface with foundries, IP vendors, and EDA tool providers to ensure efficient design execution.
  • Mentor and lead a team of ASIC designers and engineers.
  • Conduct design reviews and provide technical guidance throughout the development cycle.
  • Contribute to ASIC product roadmap and technology strategy.
Required Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC design, with a strong focus on high-performance computing or AI accelerators.
  • Expertise in RTL design (Verilog/SystemVerilog), synthesis, and timing closure.
  • Deep understanding of memory architectures, on-chip interconnects, and low-power design techniques.
  • Hands-on experience with industry-standard EDA tools for logic synthesis, simulation, and verification.
  • Knowledge of high-speed interfaces (PCIe, HBM, DDR, etc.).
  • Experience in chip bring-up, lab validation, and silicon debug.
  • Proven leadership experience, with a track record of successfully delivering ASIC products.
Preferred Qualifications:
  • Advanced degree in Electrical or Computer Engineering.
  • Experience with AI/ML workloads and deep learning accelerators.
  • Familiarity with RISC-V, GPU, or other parallel computing architectures.
  • Experience implementing Customer Owned Tooling (COT) integrated circuits.
  • Understanding of software-hardware co-design for AI inference optimization.
Why Join Us?
  • Be part of an early-stage startup defining the future of AI inference hardware.
  • Opportunity to work on groundbreaking technology with a highly talented team.
  • Competitive salary, equity, and comprehensive benefits package.
  • Flexible work environment with remote work options.

If you are excited about pushing the boundaries of AI hardware and leading a world-class ASIC design team, we want to hear from you! Apply today.


Top Skills

Verilog,Systemverilog
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The Company
HQ: Reno, NV
42 Employees
Year Founded: 2023

What We Do

Positron delivers vendor freedom and faster inference for both enterprises and research teams, by allowing them to use hardware and software explicitly designed from the ground up for generative and large language models (LLMs).

Through lower power usage and drastically lower total cost of ownership (TCO), Positron enables you to run popular open source LLMs to serve multiple users at high token rates and long context lengths. Positron is also designing its own ASIC to expand from inference and fine tuning to also support training and other parallel compute workloads.

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