Applications Engineering Manager for Physical Design/Testchip

Job Details:

Job Description: 

About Foundry Technology Development:

Technology Development (TD) is the heart and soul of Moore’s Law at Intel. TD has enabled Intel to create world-changing technology that enriches the lives of every person on earth. TD’s more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.

About the Role:

At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DTP cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs.
The Engineering Manager position within the Design Enablement (DTP) organization of Technology Development (TD) is chartered as an Applications and Support Manager position leading a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets , Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.
Responsibilities

• Set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance.
• Plan, provide resources for and direct activities in engineering function to meet schedules, standards, and cost.
• Cultivate and reinforce appropriate group values, norms and behaviors. Identify and analyze problems, plans, tasks, and solutions.
• Provide guidance on employee development, performance, and productivity issues.
• Plan and schedule daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.

Candidate must exhibit the following behavioral traits/skills:

• Drive a customer-oriented culture in the team and provide with fast response times to user issues and concerns.
• Demonstrate experience in analytical problem-solving capability and teamwork with ability to work across organizational boundaries.
• Proven leadership skills, influencing skills and communication skills.

Required Skills/Experience

8+ years of experience in two or more of the following:

• Technical management experience managing medium sized teams.
• Experience with Test chip physical verification and tape-in Intel and/or external foundry process technology knowledge in advance nodes
• Industry direct experience and in depth knowledge to support customers in ASIC/Physical Design and/or Physical Verification/runsets, in advanced technology nodes, or EDA tools.
• Ability to understand the technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.

Preferred Skills/Experience

• Experience in using industry standard software engineering principles
• Demonstrate ability to drive changes towards industry standard practices and methodologies.

Qualifications:

BS degree in Electrical Engineer or Computer Engineering or related field with 20+ years of experience

OR

MS degree with 18+ years of experience

OR

PhD degree with 15+ years of experience.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$228,130.00-$322,070.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.