Principal Analog Design Engineer

Location: Camarillo or San Jose, California

Our Team:

Semtech Corporation is a leading global supplier of analog and mixed-signal semiconductors and advanced algorithms for high-end consumer, enterprise computing, communications, and industrial equipment. As our opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading-edge products.

Job Summary:

We are seeking a Power MOSFET Engineer with expertise in vertical FET architectures to lead the design, development, and optimization of high-efficiency power devices. The ideal candidate will have experience with vertical MOSFET structures, semiconductor device physics, and fabrication processes. Reporting directly to the Design Engineering Manager and interfacing with Applications, Marketing, Packaging, and Integration Engineers. The Design Engineer is responsible for all phases of new product development lifecycle from market definition through to production release. This includes the definition, design and simulation, validation, and qualification of new products throughout the range of protection requirements ranging from ESD threats in today’s portable electronic devices, through lightning threats to servers and communications infrastructure.

Responsibilities:

• Responsible for all phases of new product development lifecycle from market definition to production release, including the definition, design and simulation, validation, and qualification of new products throughout the range of protection requirements.
• Design and develop high-performance power MOSFETs (VDMOS, superjunction, or SiC/GaN) for high-performance applications such as transient suppressor and power management.
• Conduct design feasibility studies based on device modelling and simulation using PSpice/Silvaco software.
• Perform device simulation, modeling, and characterization to optimize efficiency, thermal performance, and reliability.
• Collaborate with process integration team to propose silicon wafer process flow and Design of Experiments (DoE) process condition for prototype trials.
• Collaborate with package design engineers to propose high performance package solution.
• Conduct failure analysis and develop strategies for performance enhancement.
• Stay up to date with emerging trends in power semiconductor technology and contribute to R&D efforts.
• Work closely with applications engineers and marketing personnel regarding new product definition and specification.
• Provide development engineering support to subcontractors, including yield analysis, transfer and set-up of new products, and technical troubleshooting of development issues.
• Communicate with product engineers, integration engineers, equipment engineers and reliability engineers to resolve technical issues and ensure an expeditious release to production.
• Ensure finished products adhere to specifications and Quality Control (QC) standards prior to release.
• Perform circuit level simulation with PDK technology including testbench setup, corner simulation, and parameter optimization.
• Conduct feasibility study on PDK technology by doing device/component level simulation.

Minimum Qualifications:

• MS or PhD in Electrical Engineering, Semiconductor Physics, or a related field. 
• Knowledge of power semiconductor devices, specifically MOSFETs, VDMOS, IGBTs, or GaN/SiC technologies.
• At least 10 years of relevant experience
• Must have good oral and written communication skills.
• Must have strong critical thinking and problem-solving skills.
• Willingness to become part of a dynamic engineering team which values growth and innovation of both products and individuals.

Desired Qualifications

• MS or PhD in Electrical Engineering, Semiconductor Physics, or a related field. 
• Qualifying experience must include 15+ years in the following areas:
  • Power Semiconductor Device
  • Transient Voltage Suppressor (TVS) Circuits (preferred)
  • Advanced Semiconductor Transistors
  • Silicon Wafer Process Flow
  • Device Characterization Data Analysis
  • PSpice/Silvaco Software
  • Design of Experiments (DoE)
• Strong knowledge of vertical power semiconductor devices, including VDMOS, superjunction MOSFETs, and SiC/GaN vertical FETs.
• Experience in device simulation tools and CAD software.
• Hands-on experience with power FET testing and characterization.
• Knowledge of power packaging technologies and thermal management for high-power devices.
• Must have good oral and written communication skills.
• Must have strong critical thinking and problem-solving skills.
• Willingness to become part of a dynamic engineering team which values growth and innovation of both products and individuals.

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace.

A reasonable estimate of the pay range for this position is $120,000 - $160,000.  There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education, and experience, as well as job location and the value of other elements of an employee’s total compensation package.