Analog Circuit Designer (Team Lead)

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute:

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

To further strengthen our team, we are looking for a hardworking principle analog design engineer who will be involved leading design of advanced high-speed analog circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. Your role as an analog designer will be to deliver advanced high-speed circuits within a larger team who are responsible for a full mixed signal IP block solution that will be integrated into the Wavelogic family of products.  These analog macros include design and delivery of optical-line-facing high-speed ADC circuits interfacing with optical modulators and detectors, and critical precision analog circuits for control and monitoring functions, etc.

In this role:

• You will be responsible to perform feasibility work with various circuit topologies to recommend the best solution to carry through implementation by weighing tradeoffs and discussing these with other members of the team to guide formation of a circuit requirement specification.
• You will be responsible for the complete and detailed design of multi-phase clock-generation and distribution. Requiring close collaboration with other members of the design team and analog layout team members as applicable who may assist with some aspects of the overall implementation through to full GDSII delivery to Ciena’s integration partner.
• Characterization in Ciena’s state-of-the art lab of the analog circuits from test-chips through to full product implementation working with members of our Analog Macro Integration team.
• Reporting on status updates on a regular basis, participation in team meetings and sharing of experience with the rest of the group.

The Must Haves:

• Electrical or computer engineering or other applicable scientific degree at the MSc or Ph.D level.
• Experience leading designs in advanced CMOS and/or BiCMOS technology.
• A highly motivated self-starter, able to work independently, while being a great teammate.
• Ability to methodically address sophisticated technical problems.
• Excellent organization, written and oral (English) interpersonal skills.
• Proficiency above the intermediate level with use of applicable design tools from Cadence, Mentor and Synopsys for analog design (eg Virtuoso, Calibre, STAR-RC, MMSIM).
• A history of successful analog circuit deliveries at mm-wave frequencies.

Assets:

• Experience with 2.5D or 3D E-M tools such as HFSS or EMX.
• Experience with team-leadership within an analog macro design group.
• Experience designing high performance clock generation and distribution circuits.
• Experience with mixed-signal design validation using state-of the art probing and test equipment.

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

Pay Range:

The annual pay range is $127,700 - $204,100.

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Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

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