Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed-signal IPs.
Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.
Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.
Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.
Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues.
Optimizes performance, power, area, and reduces leakage of circuits.
Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.
Lead and plan the design and development tasks of IP independently , guide junior engineers on R&D tasks , work with cross functional teams on IP development.
BSEE/MSEE/PhD in Electrical Engineering or equivalent with a minimum of 12 years of experience in analog/mixed signal design or high speed IO/high voltage IO designs including transmitter, receiver and voltage regulator.
Direct design experience with analog and mixed signal circuits like amplifiers, comparators, regulators, IO, PLL etc
Nice to have design experience of high speed analog and mixed-signal design, architecture, system and integration aspects for AIB/UCIe, HBM PHYs, DDR/LPDDR/MIPI interfaces as well as LVDS/GPIO designs.
Solid understanding of analog design trade-offs and design for process variation and reliability in modern CMOS technologies
Hands on experience with analog simulation and reliability tools and flows
Understanding of Verilog, static timing analysis, UPF and related aspects of mixed signal design
Good communication and presentation skills to enable cross functional collaboration
Effective prioritization and planning, time management skills
Be willing to work in a dynamically changing, cross geo environment which requires ingenuity and skills to solve issues
Team player - Be willing to work autonomously, and also collaboratively in a team environment
Leadership - Expect to lead a small team of engineers for R&D task and work with cross functional teams independently .
Skills Required
- BSEE/MSEE/PhD in Electrical Engineering
- Minimum of 12 years of experience in analog/mixed signal design
- Direct design experience with amplifiers, comparators, regulators, IO, PLL
- Experience with high speed analog/mixed-signal design
- Hands on experience with analog simulation and reliability tools
- Good communication and presentation skills
- Leadership experience in a team environment
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
