Responsible for CMOS custom circuit design and validation for high speed IO buffer.
Involve in entire design cycle including spec definition, architecture definition, design implementation, circuit/functional validation and all the way to support silicon correlation.
Work with Product Architecture team on architecture and process evaluation for new product or new IO buffer design. Perform competitive analysis vs competitors.
High speed IO buffer circuit design including DDR IO, LVDS IO and high voltage (3V) IO as well as supporting logics like Vref, OCT, ESD and etc.
Circuit simulation and verification using industry simulator such as SPICE sim. Logic/functional validation using VCS or logic equivalency checker
Support layout floorplanning and layout review to produce quality and reliable layout
BS/MS in Electronics Engineering.
CMOS circuit design basic knowledge and understanding.
Knowledge and/or experience in front-end (RTL & synthesis) design would be an added advantage.
Strong in communication, leadership, problem solving and analytical skills.
Top Skills
What We Do
Altera: Accelerating Innovators
Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
