Agentic AI Engineer

Agentic AI Engineer 

Role Summary

Cadence is hiring early-career Agent AI Engineers to join our applied AI team building agentic systems for silicon design. You will work alongside senior AI engineers and chip-design domain experts on the core technical pillars of Cadence's agentic stack: training and adapting models for engineering tasks, engineering high-quality design context (RAG, prompt scaffolds, retrieval pipelines), and tuning the knowledge graphs and vector/graph databases that ground our agents. From day one you will be writing production code that lands in customer-facing AI products and directly accelerates how the world designs chips.

What You Will Do

• Model Development. Train, fine-tune, distill, and evaluate LLMs / SLMs and embedding models for EDA-specific tasks. Hands-on with LoRA / PEFT, instruction tuning, preference optimization (DPO/GRPO), and rigorous eval harnesses for code and reasoning.
• Design Context Engineering. Build the retrieval pipelines, prompt scaffolds, and tool-calling specs that feed Cadence agents the right design context (RTL, scripts, logs, reports, methodology docs) at the right token budget. Optimize for accuracy, latency, and cost.
• Knowledge Graph & Database Tuning. Design schemas, tune ingestion, and optimize queries for graph DBs (Neo4j, ArangoDB, NebulaGraph) and vector stores (Qdrant, Weaviate, pgvector, Chroma). Keep retrieval fast, accurate, and scoped to the right design hierarchy.
• Agent Building Blocks. Implement and harden agent tools, memory, multi-hop reasoning patterns, and guardrails. Triage production failures and iterate.
• Data Pipelines. Curate, clean, and label datasets from EDA artifacts (RTL, waveforms, logs, reports, schematics). Build synthetic-data and self-improvement loops where appropriate.
• Evaluation & Telemetry. Build offline benchmarks and online metrics. Help define what 'good' looks like for chip-design agents and keep regressions out of main.
• Collaborate & Learn. Pair with senior AI engineers, BU teams, and silicon domain experts. Learn the EDA flow as you go - we'll invest in you if you invest in the craft.

Must-Have Qualifications

• BS / MS / PhD in CS, EE, ECE, AI/ML, or a closely related field (graduating in 2025-2026; recent grads also welcome).
• Strong fundamentals in deep learning, transformers, and modern LLM mechanics (attention, tokenization, context windows, decoding).
• Practical hands-on experience (coursework, internships, OSS, or serious side projects) with at least TWO of: LLM fine-tuning, RAG / retrieval, agentic frameworks, knowledge graphs, vector databases.
• Solid Python engineering: comfortable with PyTorch and Hugging Face; writes clean, tested, version-controlled code.
• Curiosity about silicon / chip design and willingness to learn a deep technical domain on the job.
• Strong written and verbal communication; bias to ship working code over perfect plans.

Nice-to-Have / Bonus

• Prior internship in AI/ML at a product company or research lab with shipped artifacts.
• Hands-on with at least one agentic framework: LangGraph, AutoGen, Cursor SDK, Claude Code, MCP-based tool-calling stacks.
• Experience with graph DBs (Neo4j, ArangoDB, NebulaGraph) and / or vector DBs (Qdrant, Weaviate, pgvector, Chroma, Milvus).
• ML systems / infra exposure: vLLM, TGI, Triton, distributed training, GPU performance tuning, quantization.
• Coursework or projects in compilers, formal methods, hardware description languages (Verilog/SystemVerilog/Chisel), or EDA tools.
• Publications, OSS contributions, or competitive ML records (Kaggle medals, MLPerf, agent benchmarks, hackathon wins).