Teams at Voltai

Own SoC, subsystem, and IP architecture from requirements through specification and tapeout. Build performance, power, and area models; define memory hierarchies, interconnects, and interfaces; and lead architecture reviews. Write specifications for RTL, verification, and physical design teams, collaborate with ML researchers on AI-assisted architecture exploration, and translate customer requirements into silicon.

Own block-level and full-chip physical implementation from netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, timing, power, congestion, physical verification, and signoff. Build automation for place-and-route flows, evaluate AI-generated physical design decisions, and collaborate with semiconductor customers on implementation challenges.

Own DFT architecture and implementation for SoCs and IP, including scan, compression, MBIST, LBIST, boundary scan, ATPG, verification, and timing closure. Support silicon bring-up, pattern debugging, yield analysis, automation, and coverage reporting. Collaborate with RTL, synthesis, physical design, test, and product engineering teams while helping develop AI-assisted DFT methodologies.