SK hynix Benefits Overview

Develops signal and power integrity solutions for next-generation SSDs, including controller package and PCB design. Responsibilities include pre- and post-layout simulation, stack-up and routing definition, design reviews, lab validation, measurement correlation, debugging, root-cause analysis, documentation, cross-functional collaboration, customer escalations, and mentoring engineers. The role focuses on high-speed PCIe, DDR, NAND, and power delivery networks.

Lead advanced-node ASIC physical design from synthesis through GDS and tapeout. Drive placement, CTS, routing, timing closure, extraction, physical verification, and power integrity signoff for high-performance SoCs. Develop automation flows, optimize power, performance, and area, resolve design-rule and reliability issues, collaborate across engineering teams, and mentor junior engineers.

Conduct research on closed-loop AI-assisted hardware/software co-design flows for SoC development. Structure, implement, and evaluate loops involving search, verification, simulation, RTL, and physical design. Apply loops to microarchitecture, RTL implementation, verification, or power-performance-area optimization. Build reliable, reproducible workflows with caching, regression checks, clear interfaces, and reporting, then document findings and recommend design-automation practices.