Teams at Silicon Labs

Develop timing constraints and signoff methodologies for low-power wireless SoCs and IP. Improve static timing analysis flows, establish timing criteria, analyze reports using scripting, and drive timing closure across global design and multifunctional teams. The role addresses complex clocking, timing corners, aging, on-chip variation, signal integrity, mixed-signal IP integration, and functional and test modes.

Lead hardware product management for IoT wireless SoCs from concept through product definition and customer alpha. Define requirements, features, specifications, system KPIs, evaluation tools, and product roadmaps across wireless protocols and embedded technologies. Collaborate with IC design, software, validation, test, marketing, applications, operations, and sales teams. Conduct competitive and die-level analysis, develop technology investment business cases, manage product portfolios, and present strategic recommendations to executives.

Leads verification of complex digital RTL blocks for wireless modem baseband and PHY-layer IPs. Develops SystemVerilog/UVM environments, testbenches, verification plans, constrained-random tests, coverage models, and C-based reference-model integrations. Performs bit-exact verification, debugs RTL and testbench issues, verifies mixed-signal datapaths, and collaborates with design, systems, and SoC teams to resolve integration challenges and deliver reliable wireless SoCs.