Teams at SiFive

Lead SWQA validation for RISC-V hardware products on pre-silicon platforms (QEMU, FPGA, RTL). Drive test strategy, automation (Python/PyTest/Robot), config management, failure triage, root-cause analysis, and cross-team coordination to improve release readiness and quality metrics.

Lead design verification for out-of-order CPU cores: own DV strategy and execution, architect SystemVerilog/UVM testbenches, develop constrained-random and scenario libraries, define coverage and assertion sign‑off, debug complex OOO and memory/coherence issues, collaborate with RTL/microarchitecture/post‑silicon teams, and mentor junior DV engineers.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.