Teams at SiFive

Own formal verification for out-of-order CPU core blocks, including test planning, property development, abstraction, proof, debugging, sign-off, assertion library maintenance, and automation. Collaborate with micro-architects, RTL designers, and verification teams while guiding colleagues on formal verification tools and techniques.

Verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout. Responsibilities include developing UVM testbench infrastructure, constrained-random and directed tests, functional coverage, assertions, regression tooling, and co-simulation flows. Debug pipeline, memory-ordering, speculation, and privilege-related failures using logs and waveforms, drive coverage closure, maintain regression health, and collaborate with micro-architects and RTL designers on verification plans and issues.

Owns formal verification strategies for complex processor modules, including identifying suitable blocks, creating test plans, implementing Chisel-based verification environments, applying formal techniques, debugging RTL, automating verification, maintaining assertion libraries, and guiding team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, and SystemVerilog.