Teams at SiFive

Design and implement features in RISC-V CPU cores, collaborate with verification and physical design teams, and document processes.

The Senior Software Quality Assurance Engineer will design and optimize CI/CD test automation pipelines, lead root cause analyses of test failures, and define key quality metrics for continuous improvement.

Lead low-power verification and optimization for RISC-V cores, driving quality closure at CPU and block levels. Collaborate with microarchitecture and RTL teams, run UPF/VCS power simulations, develop UVM testbenches, mentor engineers, and support test planning and execution for new features.