Teams at SiFive

Provide senior-level technical escalation and debugging for complex digital physical design issues across the RTL-to-GDSII flow. Guide customers on PD recipes to meet PPA targets, develop reference documentation and application notes, and collaborate with support, account, and R&D teams to improve tools and flows for successful tape-out.

Lead power integrity signoff for high-speed CPUs: define IR signoff criteria, architect power grids and bump maps, drive IR drop flow automation, and integrate PrimeTime-PX power readouts while collaborating with Physical Design and Power teams.

Lead verification planning and execution for CPU subsystems, develop scalable testbenches, assertions, coverage, and constrained-random tests. Drive failure analysis, debug RTL/spec/test content issues, close coverage gaps, and improve verification methodology and automation across CPU designs.