Teams at SiFive

Lead end-to-end design verification for complex CPU cores, including fetch, decode, execution, memory, pipelines, caches, and MMUs. Develop verification strategies, test plans, UVM testbenches, constrained-random tests, scoreboards, checkers, and functional/code coverage models. Validate out-of-order execution, branch prediction, cache coherency, virtual memory, paging, exceptions, interrupts, and ISA compliance. Drive regressions, debug simulation and emulation failures, and partner with architecture and design teams to achieve verification closure.

Provides senior technical support for complex semiconductor physical design issues from RTL synthesis through place-and-route and post-route signoff. Responsibilities include debugging EDA tool and implementation problems, optimizing power, performance, and area targets, developing reference flows and technical documentation, and communicating customer feedback to internal engineering and R&D teams.

Lead end-to-end physical implementation of high-speed NoC and Uncore subsystems from RTL to GDSII. Drive architecture and physical-design co-optimization, floorplanning, macro placement, timing closure, routability, clock and reset distribution, and PPA improvements on advanced FinFET nodes. Develop implementation methodologies and automation, solve interconnect challenges, and mentor engineers while partnering with RTL and architecture teams.