Teams at SambaNova Systems

Develop and execute chip-level verification plans for SambaNova’s RDU AI processor. Build SystemVerilog and UVM testbenches, sequences, checkers, assertions, and coverage. Create directed and constrained-random tests, run regressions, debug simulation failures with RTL designers, and analyze coverage gaps before tape-out.

Train and evaluate machine learning models that improve large language model inference efficiency and capability. Responsibilities include speculative decoding, quantization, sparsity, distillation, pruning, parameter-efficient fine-tuning, agentic systems, benchmarking, research implementation, and reinforcement learning or post-training. The role collaborates with performance, compiler, runtime, and product teams to ship model improvements.

Run and improve RTL-to-GDS physical design flows on advanced process nodes. Perform synthesis and place-and-route using Cadence tools, automate workflows with Tcl and Python, debug timing, congestion, and design-rule issues, support tool-vendor bug resolution, and maintain documentation and regression testing.