Teams at nEye Systems

Lead code-first layout design and tapeout of complex Silicon Photonics PICs. Build and maintain a parametric Python function library, automate optical routing, DFT insertion, and full-chip assembly for HVM. Drive DRC/LVS cleanup with Calibre/KLayout, integrate version control and Layout CI, and translate foundry rules into layout constraints to maximize yield.

Responsible for architecting and managing nEye's supply chain, including vendor engagement, materials planning, logistics, and systems implementation for a hardware company.

The Test Engineer will lead silicon photonics system testing, develop methodologies, automate tests, troubleshoot issues, and document findings.