Jobs at NextSilicon

Act as primary technical liaison for HPC customers: troubleshoot and reproduce issues, optimize parallel applications, profile performance across architectures, drive product features through customer engagement, maintain documentation, and advocate customer needs to engineering teams.

Lead porting and performance analysis of HPC applications at node and at scale. Profile bottlenecks, design algorithmic and software optimizations for a novel dataflow architecture, translate application needs into software features and hardware requirements, and build performance models for future architectures.

Provide hands-on technical support for HPC scientific applications, troubleshoot and reproduce client issues, profile and optimize parallel code, and drive product improvements through customer engagement and collaboration with engineering and product teams. Maintain documentation and act as a liaison between customers and internal stakeholders to translate needs into features.

Design and implement virtualization support for RISC-V architecture, ensuring compliance and optimization of the software stack for performance in virtualized workloads.

Manage the complete program lifecycle of hardware development, from architecture to tapeout, ensuring quality, scope, and schedule are met.

Develop, optimize, and productionize mathematical algorithms for a general-purpose coprocessor. Explore graph theory and clustering approaches, analyze application code and performance data, and collaborate cross-functionally to translate research into practical high-performance computing solutions.

Develop a toolchain and compiler stack for next-generation hardware, focusing on backend development within the LLVM compiler and low-level optimizations.

Develop and optimize compiler analyses and transformations for an adaptive runtime targeting NextSilicon hardware. Contribute to MLIR/LLVM upstream, benchmark HPC applications, identify optimization opportunities, and collaborate with software, HPC application, and hardware teams to improve performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on custom hardware. Contribute to upstream MLIR/LLVM, benchmark applications, identify optimization opportunities, and collaborate with software, hardware, and application teams to drive runtime compiler performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on specialized hardware. Contribute to upstream MLIR and LLVM, develop an adaptive runtime compiler, benchmark applications to identify optimization opportunities, and collaborate with software, HPC, and hardware teams.

Administer, provision, and maintain HPC/AI compute, storage, networking, and software stacks. Develop automation for provisioning, configuration management, and monitoring. Install, configure, and optimize job schedulers (e.g., Slurm), deploy MPI and containerized HPC applications, perform benchmarking, tuning, capacity planning, security patching, troubleshooting, and vendor coordination while supporting researchers and documenting procedures.

The Senior Logic Design Engineer will design advanced blocks for chips, transform architectural requirements into specifications, and optimize power while collaborating with teams on execution.

As an AI Workloads Engineer, you'll model AI workflows on NextSilicon hardware, run open-source systems, and drive performance improvements.

Develop an MLIR-based AI compiler stack targeting next-generation hardware, while collaborating with various teams to enhance AI applications.

Develop a compiler stack for parallel frameworks and improve NextSilicon's software stack by collaborating with multiple teams.

The role involves physical design engineering, leading backend initiatives and working collaboratively on advanced HPC product designs, focusing on critical performance metrics and methodologies.

The role involves developing a runtime compiler for accelerating HPC and AI applications, requiring collaboration with hardware teams and designing APIs for integration.

The engineer will optimize AI libraries and components for unique hardware, focusing on performance improvements in AI models and kernels.

The AI Compiler Engineer will develop the AI graph compiler and work on the software stack to optimize AI models for unique hardware architecture. Responsibilities include enhancing performance for AI models and contributing to related components in the software stack.

Lead physical design projects, collaborating with teams to meet challenges in area, timing, and layout. Ensure robust verification and implementation of methodologies.