Jobs at NextSilicon

Builds and scales production and staging infrastructure, CI/CD systems, automation frameworks, and deployment environments. Supports engineering teams, manages Kubernetes environments, troubleshoots incidents, improves DevOps processes, and implements infrastructure automation. The role also requires monitoring and logging expertise, collaboration with development teams, and solving complex infrastructure and technology problems.

Lead the architecture and execution of next-generation HPC and AI chips. Manage managers and technical leads while remaining hands-on in architectural decisions, system-level design, technical execution, milestone delivery, and cross-functional collaboration with software, architecture, verification, and backend engineering teams. Build group expertise, define execution indicators, monitor progress, and support prioritization and decision-making.

Lead the architecture and execution of future high-performance computing and AI chips. Manage managers and technical leads while remaining hands-on in system-level architecture, technical decisions, milestone delivery, and front-end design analysis. Translate requirements into specifications, guide high-speed and low-power digital design, build team expertise, collaborate with software, verification, architecture, and back-end teams, and monitor execution indicators to support prioritization and decision-making.

Develop, optimize, and productionize mathematical algorithms for a general-purpose coprocessor. Explore graph theory and clustering approaches, analyze application code and performance data, and collaborate cross-functionally to translate research into practical high-performance computing solutions.

Develop a toolchain and compiler stack for next-generation hardware, focusing on backend development within the LLVM compiler and low-level optimizations.

Develop and optimize compiler analyses and transformations for an adaptive runtime targeting NextSilicon hardware. Contribute to MLIR/LLVM upstream, benchmark HPC applications, identify optimization opportunities, and collaborate with software, HPC application, and hardware teams to improve performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on custom hardware. Contribute to upstream MLIR/LLVM, benchmark applications, identify optimization opportunities, and collaborate with software, hardware, and application teams to drive runtime compiler performance.

Design, implement, test, and maintain high- and low-level compiler optimizations and analyses for HPC applications on specialized hardware. Contribute to upstream MLIR and LLVM, develop an adaptive runtime compiler, benchmark applications to identify optimization opportunities, and collaborate with software, HPC, and hardware teams.

Administer, provision, and maintain HPC/AI compute, storage, networking, and software stacks. Develop automation for provisioning, configuration management, and monitoring. Install, configure, and optimize job schedulers (e.g., Slurm), deploy MPI and containerized HPC applications, perform benchmarking, tuning, capacity planning, security patching, troubleshooting, and vendor coordination while supporting researchers and documenting procedures.

The Senior Logic Design Engineer will design advanced blocks for chips, transform architectural requirements into specifications, and optimize power while collaborating with teams on execution.

As an AI Workloads Engineer, you'll model AI workflows on NextSilicon hardware, run open-source systems, and drive performance improvements.

Develop an MLIR-based AI compiler stack targeting next-generation hardware, while collaborating with various teams to enhance AI applications.

Develop a compiler stack for parallel frameworks and improve NextSilicon's software stack by collaborating with multiple teams.

The role involves physical design engineering, leading backend initiatives and working collaboratively on advanced HPC product designs, focusing on critical performance metrics and methodologies.

The role involves developing a runtime compiler for accelerating HPC and AI applications, requiring collaboration with hardware teams and designing APIs for integration.

The engineer will optimize AI libraries and components for unique hardware, focusing on performance improvements in AI models and kernels.

The AI Compiler Engineer will develop the AI graph compiler and work on the software stack to optimize AI models for unique hardware architecture. Responsibilities include enhancing performance for AI models and contributing to related components in the software stack.

Develop a new communication stack, including network drivers and user-space libraries, focused on low-latency applications and collaboration with hardware teams.

Lead physical design projects, collaborating with teams to meet challenges in area, timing, and layout. Ensure robust verification and implementation of methodologies.

Lead the design of advanced RISC-V CPU ASICs, drive execution across teams, and ensure successful tape-out and product bring-up. Requires 6+ years experience in ASIC design.