Teams at Microchip Technology Inc.

Leads architecture, microarchitecture, RTL design, synthesis, sign-off, and silicon bring-up for complex data-center ASICs. Serves as a digital design authority, resolving EDA and cross-domain challenges while optimizing performance, power, and area. Collaborates with verification, physical design, DFT, systems, and product teams; influences PCIe, CXL, NVMe, and SAS roadmaps; and mentors engineers. Requires extensive ASIC/SoC experience, multiple tape-outs, low-power methodologies, DFT, scripting, and high-speed protocol expertise.

Develop and maintain in-house and external foundry Process Design Kits, integrating simulation, physical verification, and parasitic extraction collateral. Automate Cadence design flows using SKILL and Linux scripting, configure design environments, and manage design data. Provide worldwide support and troubleshooting for Cadence capture and layout tools, deliver user training, and maintain web-based documentation. Requires at least five years of relevant custom IC design, PDK, Cadence Virtuoso, and scripting experience.

Administers, supervises, reports on, and improves manufacturing equipment, tooling, logistics, and assembly-line operations. Supports major equipment downtime, preventive maintenance, and calibration activities. Develops manufacturing methods and processes, coordinates new product and equipment releases, estimates manufacturing costs, establishes time standards, recommends tooling and equipment, and maintains operational records and reporting systems.