Teams at MemryX

Leads development of next-generation AI accelerator chips from architecture and RTL through tapeout, silicon bring-up, qualification, and production. Oversees hardware engineering teams, ASIC program execution, technical tradeoffs, design reviews, external semiconductor partners, and hardware/software co-design. Collaborates with architecture, software, systems, product, and executive teams while managing risks, milestones, manufacturing considerations, and organizational growth.

Define and drive system-level architectures for next-generation AI and edge-computing SoCs. Responsibilities include specifying memory, interconnect, coherency, I/O, security, and power architectures; evaluating performance, power, area, cost, and schedule tradeoffs; modeling AI workloads; guiding cross-functional RTL, verification, firmware, compiler, and application teams; and supporting validation, silicon bring-up, characterization, and optimization.

Define and lead system-level architectures for next-generation AI and edge-computing SoCs. Responsibilities include memory hierarchy, IP, interconnect, coherency, I/O, security, power management, specifications, performance modeling, PPA tradeoff analysis, and collaboration with RTL, verification, firmware, compiler, and applications teams through silicon bring-up.