Teams at Marvell Technology

Lead and own end-to-end subsystem design verification: define DV processes, architect and implement UVM/C testbenches, develop and execute test plans, collaborate across IP/SoC teams, debug simulation failures, drive coverage closure and support post-silicon bring-up.

Lead verification architecture, execution, and delivery for next-generation ASICs. Drive emulation, post-silicon validation, lab bring-up, and PSV. Guide verification methodologies, tools, and front-end ASIC processes. Collaborate cross-functionally, lead teams, and ensure successful tapeout and high-quality ASIC products.

Responsible for defining and implementing IT PMO strategy, managing project portfolios, overseeing program execution, and optimizing financial resources while ensuring stakeholder alignment and compliance with governance frameworks.