Teams at Marvell Technology

Leads DFT architecture, implementation, validation, timing analysis, pattern generation, and post-silicon bring-up for complex mixed-signal SoCs. Defines and improves DFT methodologies and tools across multiple chip generations, while mentoring and guiding a team of DFT engineers. Requires deep experience with SCAN, MBIST, IP-DFT, STA, DFX, ASIC design flows, and industry-standard Cadence, Mentor, and Synopsys tools.

Staff DFT Engineer responsible for implementing scan, compression, OCC, wrappers, and MBIST; running ATPG, DFT DRC, simulations, and coverage analysis; supporting timing closure and silicon bring-up; debugging ATE patterns; and automating DFT flows with scripts. The role requires collaboration with physical design and STA teams on advanced ASIC programs.

Define and implement DFT architecture for complex SoCs, including hierarchical DFT, scan, compression, ATPG, MBIST, JTAG, and at-speed testing. Lead DFT sign-off, timing and equivalence checks, silicon debug, failure diagnosis, yield learning, and handoff to physical design and ATE teams. Mentor engineers, coordinate cross-functionally, and improve DFT methodology and automation for advanced-node optical DSP products.