Marvell Technology Benefits Overview

Design, implement, verify, and document micro-architecture and RTL for complex power-management ASICs. Own end-to-end development from architecture and RTL coding to synthesis, timing closure, formal and gate-level verification, silicon bring-up, documentation, and cross-functional reviews while improving design and verification methodologies.

Develop and maintain UVM/SystemVerilog SoC-level verification environments and testbenches. Create test plans and strategies to meet coverage goals, develop tests, debug failures, and collaborate with designers to resolve issues across complex SoC architectures.

Lead digital SoC integration and RTL design efforts, owning portions of chip design through tape-out. Perform RTL development in SystemVerilog, run functional and gate-level simulations, handle CDC, timing closure, clock/reset design, post-silicon debug, and collaborate across architecture, physical design, verification, DFT, and packaging. Deliver micro-architectural specs, develop automation, and use scripting (Python/Tcl) and EDA tools to accelerate development.