Marvell Technology Benefits Overview

Integrate and manage third-party memory interface IP across SoC development, from requirements and supplier oversight through integration, compliance, testing, and silicon validation. Advise design centers, lead provider reviews, manage statements of work and issue resolution, support bids, and assist with supplier 8D actions. The role requires expertise in DDR-family interfaces, ASIC design flows, DFT, timing, packaging, customer management, and limited post-silicon travel.

Designs and develops synthesizable RTL for digital ICs, translating architecture into Verilog/SystemVerilog IP blocks and subsystems. Performs linting, CDC, low-power, timing, area, and power analysis; supports synthesis and timing closure. Debugs issues through simulation, emulation, FPGA prototyping, and silicon bring-up. Owns major sub-circuit blocks, investigates model-to-hardware correlation, contributes innovative optimizations, and mentors less experienced engineers.

Provides technical leadership for semiconductor product development and new product introduction through production. Leads silicon characterization, debug, qualification, risk assessment, root cause analysis, and readiness activities. Defines quality, reliability, performance, and cost targets; applies data analytics and statistics to improve yield and product quality. Aligns cross-functional engineering and operations teams, communicates technical recommendations to executives and customers, and supports scalable productization.