Marvell Technology

HQ
Santa Clara
Total Offices: 30
6,500 Total Employees
Year Founded: 1995

Marvell Technology Benefits Overview

Compensation + Benefits

Offers disability insurance

Provides a pension

Offers life insurance

Offers generous parental leave

Offers performance bonuses

Company Culture

Utilizes a flexible work schedule

Offers a remote work program

Provides free snacks and drinks

Work-Life Balance + Wellbeing

Offers generous PTO

Provides bereavement leave

Provides paid sick days

Offers unpaid extended leave

Offers gym membership

27 Minutes AgoSaved
In-Office
9 Locations
Artificial Intelligence • Automotive • Semiconductor
Ph.D. interns apply machine learning and AI to semiconductor chip design or enterprise engineering tools. Responsibilities include developing ML models for EDA automation, placement, timing, power, and verification, or deploying LLM, RAG, and agentic systems. Interns will train, evaluate, and deploy models, conduct rigorous experiments, collaborate with engineering and technology stakeholders, assess production performance and safety, and present findings to leadership. The role requires doctoral research in AI, machine learning, computer science, electrical engineering, data science, or a related field.
Artificial Intelligence • Automotive • Semiconductor
Ph.D. interns design, simulate, characterize, and validate silicon photonics components, optical engines, and DSP algorithms for PAM4 and coherent optical transceivers. Responsibilities include optical system modeling, link budget analysis, lab testing, silicon bring-up, and collaboration with analog IC, packaging, and systems engineering teams. Interns present research findings and design results while contributing to production-scale optical communications solutions.
4 Hours AgoSaved
Remote
Hsinchu City, TWN
Artificial Intelligence • Automotive • Semiconductor
Lead transition and sustainment of silicon photonics and optical transceiver products from NPI to volume production. Collaborate with US and CM teams to improve yield, implement in-process controls, manage production risks, and perform failure analysis at chip/SiPho and optical subassembly levels while owning product lifecycle activities.