Teams at Lumai

Build and own Python-based performance and power modelling frameworks for photonic AI hardware. Model concurrency, event-driven behavior, compute, memory, interconnects, and accelerator blocks; characterize AI workloads against hardware and RTL results; consume MLIR and compiler outputs; analyze simulation traces and benchmarks; validate power models; maintain CI/CD and simulation flows; and guide architecture and compiler decisions while developing future team members.

Own full-custom analog and mixed-signal layout for advanced CMOS blocks, applying precision matching, parasitic mitigation, floorplanning, and physical verification techniques. Drive DRC, LVS, PEX, ESD, and latch-up sign-off through tapeout, collaborate with circuit designers on back-annotated simulations, support post-silicon debug, and mentor junior engineers.

Design and maintain firmware, drivers, and RTOS-based control software for an AI accelerator. Lead BSP bring-up, implement deterministic RTOS tasks, debug hardware with JTAG/oscilloscope/logic capture, and establish coding standards and testing practices.