Teams at Lumai

Lead end-to-end analog and mixed-signal ASIC design for a photonic AI accelerator: architect circuits (TIA, VGA, ADC/DAC, PLLs, LDOs), drive full-custom flow and tapeout sign-off, run silicon bring-up and characterization, define design methodologies, and mentor junior designers while collaborating with photonics, digital, firmware, and foundry partners.

Own and operate end-to-end ML pipelines from research to hardware-validated production. Build experiment tracking, CI/CD, benchmarking, observability, and resource scheduling for on-prem accelerator clusters and cloud. Collaborate with ML researchers, compiler and hardware teams to optimise models, automate testing, and enable reproducible, hardware-in-the-loop deployments.

Design and maintain firmware, drivers, and RTOS-based control software for an AI accelerator. Lead BSP bring-up, implement deterministic RTOS tasks, debug hardware with JTAG/oscilloscope/logic capture, and establish coding standards and testing practices.