Lattice Semiconductor Benefits Overview

Owns and advances FPGA CAD/EDA methodologies for static timing analysis, timing abstraction, place and route, physical implementation, signoff, and design QA. Develops automated EDA flows, supports advanced-node designs, drives timing and physical closure, validates ETM/QTM models, resolves tool and technology issues, mentors engineers, and aligns methodology across global design teams.

Design, integrate, validate and deploy FPGA-based system solutions across verticals (Vision/AI, server security, industrial automation, communications, automotive). Work with customers and internal FPGA, SW/FW and data science teams to define requirements, tune performance, plan and execute validation, analyze test results, and resolve system-level issues.

Develop and review verification test plans for complex IP, build scalable UVM-based constrained-random environments, create tests and coverage mechanisms, debug design issues, drive coverage closure and sign-off, and collaborate with cross-functional engineering teams. The role also contributes to verification methodology, automation, and best practices.