Teams at Kepler

Leads end-to-end memory controller architecture and RTL design through tapeout. Owns low-latency, high-bandwidth memory interfaces, PPA optimization, verification planning, timing closure, and physical implementation issue resolution. Partners across architecture, physical design, and validation teams; establishes design practices and mentors engineers. Requires deep expertise in memory scheduling, ECC, refresh, power management, training, performance modeling, advanced VLSI trade-offs, and multiple full-chip SoC tapeouts.

Leads full-chip physical design for memory products from netlist ingestion through GDSII signoff and tapeout. Owns floorplanning, clock-tree synthesis, routing, timing closure, power-grid strategy, IR drop, electromigration, physical verification, and low-power implementation. Directs methodology, flow development, team planning, resource allocation, milestone reviews, and cross-functional integration with architecture, DFT, packaging, and manufacturing teams. Requires extensive ASIC/SoC experience, multiple successful tapeouts, advanced process expertise, and leadership in fast-paced environments.